Datasheet

TSB81BA3E
www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010
Designing With PowerPAD™ Devices (PFP Package Only)
The TSB81BA3E is housed in a high performance, thermally enhanced, 80-terminal PFP PowerPAD™ package.
Use of the PowerPAD™ package does not require any special considerations except to note that the
PowerPAD™, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical
conductor. Therefore, if not implementing PowerPAD™ PCB features, the use of solder masks (or other
assembly techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD™ of
connection etches or vias under the package. The recommended option, however, is to not run any etches or
signal vias under the device, but to have only a grounded thermal land as explained below. Although the actual
size of the exposed die pad may vary, the maximum size required for the keepout area for the 80-terminal PFP
PowerPAD™ package is 10 mm × 10 mm. The actual PowerPAD™ size for the TSB81BA3E is 6 mm × 6 mm.
It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the
PowerPAD™ package. The thermal land varies in size, depending on the PowerPAD™ package being used, the
PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may
not contain numerous thermal vias depending on PCB construction.
Other requirements for thermal lands and thermal vias are detailed in the Texas Instruments PowerPAD™
Thermally Enhanced Package application report (SLMA002) available via the Texas Instruments web page at
http://www.ti.com.
Figure 9. Example of a Thermal Land for the TSB81BA3E PHY
The thermal land must be grounded to the low-impedance ground plane of the device. This improves not only
thermal performance but also the electrical grounding of the device. It is also recommended that the device
ground terminal landing pads be connected directly to the grounded thermal land. The land size ought to be as
large as possible without shorting the device signal terminals. The thermal land can be soldered to the exposed
thermal pad using standard reflow soldering techniques.
While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is
recommended that the thermal land be connected to the low impedance ground plane for the device. More
information may be obtained from the TI application note PHY Layout (SLLA020).
Using the TSB81BA3E with a Non-1394b Link Layer
The TSB81BA3E implements the PHY-LLC interface specified in the 1394b Supplement. This interface is based
on the interface described in Section 14 of IEEE P1394b (draft 1.33). When using a LLC compliant with this
interface, the BMODE input must be tied high.
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