Datasheet

TSB81BA3E
SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com
Table 2. Base Register Field Descriptions (continued)
FIELD SIZE TYPE DESCRIPTION
Number of ports. For the TSB81BA3E, this field indicates the number of ports implemented in the
Num_Ports 4 Rd
PHY. This field is 3.
PHY speed capability. For the TSB81BA3E, this field is no longer used. This field is 111b. Speeds
PHY_Speed 3 Rd
for 1394b PHYs must be checked on a port-by-port basis.
PHY repeater data delay. This field indicates the worst-case repeater data delay of the PHY,
expressed as 144+ (delay × 20) ns. For the TSB81BA3E, this field is 02h.
This value is the repeater delay for the S400B case, which is slower than the S800B or 1394a
Delay 4 Rd cases. Since the IEEE 1394B−2002 Std Phy register set only has a single field for the delay
parameter, the slowest value is used. If a network uses only S800B or 1394a connections, then a
delay value of 00h may be used. The worst case Phy repeater delay is 197 ns for S400B and 127
ns for S800B cable speeds (trained, raw bit speed).
Link-active status control. This bit controls the indicated active status of the LLC reported in the
self-ID packet. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9)
of the self-ID packet. The LLC bit in the node self-ID packet is set active only if both the LPS input is
active and the LCtrl bit is set.
The LCtrl bit provides a software-controllable means to indicate the LLC self-ID active status in lieu
LCtrl 1 Rd/Wr of using the LPS input terminal.
The LCtrl bit is set to 1 by hardware reset and is unaffected by bus reset.
NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the
state of the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being
active, then received packets and status information continue to be presented on the interface, and
any requests indicated on the LREQ input are processed, even if the LCtrl bit is cleared to 0.
Contender status. This bit indicates that this node is a contender for the bus or isochronous
resource manager. This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to 0
C 1 Rd/Wr
on hardware reset. After hardware reset, this bit can only be set via a software register write. This
bit is unaffected by a bus reset.
PHY repeater jitter. This field indicates the worst-case difference between the fastest and slowest
Jitter 3 Rd
repeater data delay, expressed as (jitter+1) × 20 ns. For the TSB81BA3E, this field is 0.
Node power class. This field indicates this node power consumption and source characteristics and
is replicated in the pwr field (bits 21–23) of the self-ID packet. This field is reset to the state
Pwr_Class 3 Rd/Wr
specified by the PC0-PC2 input terminals upon a hardware reset, and is unaffected by a bus reset.
See Table 9.
Watchdog interrupt enable. This bit, if set to 1, enables the port event interrupt (PIE) bit to be set
when resume operations begin on any port, or when any of the CTOI, CPSI, or STOI interrupt bits
WDIE 1 Rd/Wr
are set and the link interface is nonoperational. This bit is reset to 0 by hardware reset and is
unaffected by bus reset.
Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 ms)
arbitrated bus reset at the next opportunity. This bit is reset to 0 by a bus reset. It is recommended
that short bus reset is the only reset type initiated by software. IEC 61883-6 requires that a node
ISBR 1 Rd/Wr initiate short bus resets to minimize any disturbance to an audio stream.
NOTE: Legacy IEEE Std 1394-1995-compliant PHYs are not capable of performing short bus
resets. Therefore, initiation of a short bus reset in a network that contains such a legacy device
results in a long bus reset being performed.
Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during
tree-ID start and might indicate that the bus is configured in a loop. This bit is reset to 0 by
hardware reset or by writing a 1 to this register bit.
If the CTOI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates
the LKON/DS2 output to notify the LLC to service the interrupt.
CTOI 1 Rd/Wr
NOTE: If the network is configured in a loop, then only those nodes that are part of the loop
generate a configuration time-out interrupt. All other nodes instead time out waiting for the tree-ID
and/or self-ID process to complete and then generate a state time-out interrupt and bus reset. This
bit is only set when the bus topology includes 1394a nodes; otherwise, 1394b loop healing prevents
loops from being formed in the topology.
Cable power status interrupt. This bit is set to 1 when the CPS input transitions from high to low,
indicating that cable power might be too low for reliable operation. This bit is reset to 1 by hardware
CPSI 1 Rd/Wr reset. It can be cleared by writing a 1 to this register bit.
If the CPSI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates
the LKON/DS2 output to notify the LLC to service the interrupt.
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