Datasheet

TSB81BA3E
www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010
APPLICATION INFORMATION
Please obtain from the TI website or your local TI representative the reference schematics, reference layouts,
debug documents, and software recommendations for the TSB81BA3E.
Internal Register Configuration
There are 16 accessible internal registers in the TSB81BA3E. The configuration of the registers at addresses 0h
through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the
paged registers) is dependent upon which 1 of 8 pages, numbered 0h through 7h, is currently selected. The
selected page is set in base register 7h. Note that while this register set is compatible with 1394a--2000 register
sets, some fields have been redefined and this register set contains additional fields.
Table 1 shows the configuration of the base registers, and Table 2 gives the corresponding field descriptions.
The base register field definitions are unaffected by the selected page number.
A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables) is
read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved.
Table 1. Base Register Configuration
BIT POSITION
ADDRESS
0 1 2 3 4 5 6 7
0000 Physical ID R CPS
0001 RHB IBR Gap_Count
0010 Extended (111b) Num_Ports (0011b)
0011 PHY_Speed (111b) SREN Delay (1111b)
0100 LCtrl C Jitter (000b) Pwr_Class
0101 WDIE ISBR CTOI CPSI STOI PEI EAA EMC
0110 Max Legacy SPD BLINK Bridge Rsvd
0111 Page_Select Rsvd Port_Select
Table 2. Base Register Field Descriptions
FIELD SIZE TYPE DESCRIPTION
This field contains the physical address ID of this node determined during self-ID. The physical-ID is
Physical ID 6 Rd invalid after a bus reset until the self-ID has completed as indicated by an unsolicited register 0
status transfer from the PHY to the LLC.
Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is
R 1 Rd
set to 1 during tree-ID if this node becomes root.
Cable-power status. This bit indicates the state of the CPS input terminal. The CPS terminal is
CPS 1 Rd normally tied to serial bus cable power through a 400-kΩ resistor. A 0 in this bit indicates that the
cable-power voltage has dropped below its threshold for ensured reliable operation.
Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The
RHB bit is reset to 0 by a hardware reset and is unaffected by a bus reset. If two nodes on a single
RHB 1 Rd/Wr
bus have their root holdoff bit set, then the result is not defined. To prevent two nodes from having
their root-holdoff bit set, this bit must only be written using a PHY configuration packet.
Initiate bus reset. This bit instructs the PHY to initiate a long (166-ms) bus reset at the next
opportunity. Any receive or transmit operation in progress when this bit is set completes before the
IBR 1 Rd/Wr bus reset is initiated. The IBR bit is reset to 0 after a hardware reset or a bus reset. Care must be
exercised when writing to this bit to not change the other bits in this register. It is recommended that
whenever possible a bus reset be initiated using the ISBR bit and not the IBR bit.
Arbitration gap count. This value sets the subaction (fair) gap, arb-reset gap, and arb-delay times.
The gap count can be set either by a write to the register, or by reception or transmission of a
PHY_CONFIG packet. The gap count is reset to 3Fh by hardware reset or after two consecutive
Gap_Count 6 Rd/Wr
bus resets without an intervening write to the gap count register (either by a write to the PHY
register or by a PHY_CONFIG packet). It is strongly recommended that this field only be
changed using PHY configuration packets.
Extended register definition. For the TSB81BA3E, this field is 111b, indicating that the extended
Extended 3 Rd
register set is implemented.
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