Datasheet

TSB81BA3E
www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010
Electrical Characteristics (continued)
Thermal Characteristics
PARAMETER TEST CONDITIONS
(1)
TYP TYP UNIT
PFP ZAJ
Package Package
Junction-to-free-air thermal
q
ja
Low K JEDEC Test Board, 1s (single signal layer), no air flow 50 88.7 °C/W
resistance
No air flow 24.8 46.2
Junction-to-free-air thermal High K JEDEC Test Board 2s2p (double
q
ja
400 LFM °C/W
resistance signal layer, double buried power plane)
200 LFM
Junction-to-case-thermal
q
jc
Cu Cold Plate Measurement Process 21.5 23.5 °C/W
resistance
Junction-to-board thermal
q
jb
EIA/JESD 51-8 8.37 27.8
resistance
Ψ
jt
Junction-to-top of package EIA/JESD 51-2 0.46 0.45 °C/W
Ψ
jb
Junction-to-board EIA/JESD 51-6 8.2 27.4 °C/W
(1) For more details, please refer to TI application note on IC Package Thermal Metrics (SPRA953A)
Switching Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
r
TP differential rise time, transmit 10% to 90%, At 1394 connector 0.5 1.2 ns
t
f
TP differential fall time, transmit 90% to 10%, At 1394 connector 0.5 1.2 ns
Setup time,
t
su
1394a-2000 50% to 50%, See Figure 2 2.5 ns
CTL0, CTL1, D1-D7, LREQ to PCLK
Hold time,
t
h
1394a-2000 50% to 50%, See Figure 2 0 ns
CTL0, CTL1, D1-D7, LREQ after PCLK
Setup time,
t
su
1394b 50% to 50%, See Figure 2 2.5 ns
CTL0, CTL1, D1-D7, LREQ to LCLK_PMC
Hold time,
t
h
1394b 50% to 50%, See Figure 2 0 ns
CTL0, CTL1, D1-D7, LREQ after LCLK_PMC
Delay time, 1394a-2000
t
d
50% to 50%, See Figure 3 0.5 7 ns
PCLK to CTL0, CTL1, D1-D7, PINT and 1394b
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