Datasheet
TSB81BA3E
SLLS783A –MAY 2009–REVISED MAY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
Driver
over recommended ranges of operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OD
Differential output voltage 56 Ω, See Figure 1 172 265 mV
Drivers enabled, speed signaling
I
DIFF
Driver difference current, TPA+, TPA–, TPB+, TPB– –1.05
(1)
1.05
(1)
mA
off
Common-mode speed signaling current, TPB+,
I
SP200
S200 speed signaling enabled –4.84
(2)
–2.53
(2)
mA
TPB–
Common-mode speed signaling current, TPB+,
I
SP400
S400 speed signaling enabled –12.4
(2)
–8.1
(2)
mA
TPB–
V
OFF
Off-state differential voltage Drivers disabled, See Figure 1 20 mV
(1) Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver
currents.
(2) Limits defined as absolute limit of each of TPB+ and TPB– driver currents.
Receiver
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
4 7 kΩ
Z
ID
Differential impedance Drivers disabled
4 pF
20 kΩ
Z
IC
Common-mode impedance Drivers disabled
24 pF
V
TH-R
Receiver input threshold voltage Drivers disabled –30 30 mV
V
TH-CB
Cable bias detect threshold, TPBx cable inputs Drivers disabled 0.6 1 V
Positive arbitration comparator threshold
V
TH+
Drivers disabled 89 168 mV
voltage
Negative arbitration comparator threshold
V
TH–
Drivers disabled –168 –89 mV
voltage
V
TH-SP200
Speed signal threshold 49 131 mV
TPBIAS-TPA common-mode voltage,
drivers disabled
V
TH-SP400
Speed signal threshold 314 396 mV
Device
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
3.3 V
DD
120 150
I
DD
Supply current
(1)
mA
Core V
DD
79
V
TH
Power status threshold, CPS input
(2)
400-kΩ resistor
(2)
4.7 7.5 V
High-level output voltage, CTL0, CTL1, D0-D7, PCLK, V
DD
= 3 to 3.6 V,
V
OH
2.8 V
LKON/DS2 outputs I
OH
= 4 mA
Low-level output voltage, CTL0, CTL1, D0-D7, PCLK,
V
OL
I
OL
= 4 mA 0.4 V
LKON/DS2 outputs
V
DD
= 3.6 V,
I
BH+
Positive peak bus holder current, D0-D7, CTL0-CTL1, LREQ 0.05 1 mA
V
I
= 0 V to V
DD
Negative peak bus holder current, D0-D7, CTL0-CTL1, V
DD
= 3.6 V,
I
BH–
–1.0 –0.05 mA
LREQ V
I
= 0 V to V
DD
TSB81BA3E ±5
Off-state output current, CTL0, CTL1, D0-D7, LKON/DS2
I
OZ
V
O
= V
DD
or 0 V mA
I/Os
TSB81BA3EI ±20
I
IRST
Pullup current, RESET input V
I
= 1.5 V or 0 V –90 –20 mA
V
O
TPBIAS output voltage At rated I
O
current 1.665 2.015 V
(1) Repeat max packet (one port receiving maximum size isochronous packet–8192 bytes, sent on every isochronous interval, S800, data
value of 0xCCCCCCCCh; two ports repeating; all ports with beta-mode connection), V
DD3.3
= 3.3 V, V
DDCORE
= 1.95 V, T
A
= 25°C.
(2) Measured at cable-power side of resistor.
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