Datasheet

TSB81BA3E
SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
PFP ZAJ
DESCRIPTION
PACKAGE PACKAGE
NAME TYPE NO. NO. I/O
Link power status input. This terminal monitors the active/power status of
the link-layer controller (LLC) and controls the state of the PHY-LLC
interface. This terminal must be connected to either the V
DD
supplying the
LLC through an approximately 1-kΩ resistor or to a pulsed output that is
active when the LLC is powered. A pulsed signal must be used when an
isolation barrier exists between the LLC and PHY (see Figure 8).
The LPS input is considered inactive if it is sampled low by the PHY for
more than an LPS_RESET time (~2.6 ms), and is considered active
otherwise (that is, asserted steady high or an oscillating signal with a low
time less than 2.6 ms). The LPS input must be high for at least 22 ns to be
observed as high by the PHY.
LPS CMOS 80 D3 I
When the TSB81BA3E detects that the LPS input is inactive, it places the
PHY-LLC interface into a low-power reset state. In the reset state, the CTL
(CTL0 and CTL1) and D (D0 to D7) outputs are held in the logic 0 state and
the LREQ input is ignored; however, the PCLK output remains active. If the
LPS input remains low for more than an LPS_DISABLE time (~26 ms), then
the PHY-LLC interface is put into a low-power disabled state in which the
PCLK output is also held inactive.
The LLC state that is communicated in the self-ID packet is considered
active only if both the LPS input is active and the LCtrl register bit is set to
1. The LLC state that is communicated in the self-ID packet is considered
inactive if either the LPS input is inactive or the LCtrl register bit is cleared
to 0.
LLC request input. The LLC uses this input to initiate a service request to
LREQ CMOS 3 E1 I
the TSB81BA3E. A bus holder is built into this terminal.
Power class programming inputs. On hardware reset, these inputs set the
PC0 66 C11
default value of the power class indicated during self-ID. Programming is
PC1 CMOS 67 A9 I
done by tying the terminals high through a 1-kΩ or smaller resistor or by
PC2 68 B8
tying directly to ground through a 1-kΩ or smaller resistor. Bus holders are
built into these terminals.
PHY clock. Provides a 98.304-MHz clock signal, synchronized with data
transfers, to the LLC when the PHY-link interface is operating in the 1394b
PCLK CMOS 5 F2 O
mode (BMODE asserted). PCLK output provides a 49.152-MHz clock
signal, synchronized with data transfers, to the LLC when the PHY-link
interface is in legacy 1394a-2000 (BMODE input deasserted).
Power-down input. A high on this terminal turns off all internal circuitry
except the cable-active monitor circuits, which control the CNA output.
PD CMOS 77 B3 I
Asserting the PD input high also activates an internal pulldown on the
RESET terminal to force a reset of the internal control logic.
PHY interrupt. The PHY uses this output to serially transfer status and
PINT CMOS 1 E3 O
interrupt information to the link when PHY-link interface is in the 1394b
mode. A bus holder is built into this terminal.
PLL circuit ground terminals. These terminals must be tied together to the
PLLGND Supply 25, 28 F8, N4 –
low-impedance circuit board ground plane.
PLL core circuit power terminals. A combination of high-frequency
decoupling capacitors near each terminal is suggested, such as paralleled
PLLVDD-
0.1 mF and 0.001 mF. An additional 1-mF capacitor is required for voltage
Supply 29, 30 N6 –
CORE
regulation. The PLLVDD-CORE terminals must be separate from the
DVDD-CORE terminals. These supply terminals are separated from the
DVDD-CORE, DVDD-3.
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