TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER Check for Samples: TSB81BA3E FEATURES 1 • • • • • • • • • • • • • Fully Supports Provisions of IEEE P1394b Revision 1.33+ at 1-Gigabit Signaling Rates Fully Supports Provisions of IEEE 1394a-2000 and 1394-1995 Standard for High Performance Serial Bus Fully Interoperable With Firewire , i.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com DESCRIPTION The TSB81BA3E provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 During packet reception the serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected and active cable ports.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com The LPS (link power status) terminal works with the LKON/DS2 terminal to manage the power usage in the node. The LPS signal from the LLC is used with the LCtrl bit (see Table 1 and Table 2 in the Application Information section) to indicate the active/power status of the LLC.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 PIN ASSIGNMENTS TPA0+ TPA0− AVDD−3.3 AGND TPB0+ TPB0− TPBIAS1 TPA1+ TPA1− AVDD−3.3 AGND TPB1+ TPB1− TPBIAS0 TPA2+ TPA2− AVDD−3.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.
TSB81BA3E www.ti.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com TERMINAL FUNCTIONS TERMINAL NAME AGND (1) AVDD-3.3 TYPE Supply Supply PFP PACKAGE ZAJ PACKAGE NO. NO. I/O 21, 40, 43, 50, 61, 62 See DGND – Analog circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. – Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 mF and 0.001 mF.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 TERMINAL FUNCTIONS (continued) TERMINAL NAME DVDDCORE TYPE Supply PFP PACKAGE ZAJ PACKAGE NO. NO. 8, 37, 65, 71 DESCRIPTION I/O D9, K9, D8 – Digital core circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 mF and 0.001 mF. An additional 1-mF capacitor is required for voltage regulation. These supply terminals are separated from the DVDD-3.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME TYPE PFP PACKAGE ZAJ PACKAGE NO. NO. DESCRIPTION I/O LPS CMOS 80 D3 I Link power status input. This terminal monitors the active/power status of the link-layer controller (LLC) and controls the state of the PHY-LLC interface.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 TERMINAL FUNCTIONS (continued) TERMINAL NAME PLLVDD3.3 RESET TYPE Supply CMOS PFP PACKAGE ZAJ PACKAGE NO. NO. 31 75 N7 A6 DESCRIPTION I/O – PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors near the terminal are suggested, such as paralleled 0.1 mF and 0.001 mF. Lower frequency 10-mF filtering capacitors are also recommended. This supply terminal is separated from the DVDD-CORE, DVDD-3.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME PFP PACKAGE ZAJ PACKAGE NO. NO. TYPE TPBIAS0 TPBIAS1 TPBIAS2 47 54 60 Cable XI Osc In 27 J12 E12 A12 N5 DESCRIPTION I/O I/O Twisted-pair bias output and signal detect input. This provides the 1.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 RECOMMENDED OPERATING CONDITIONS 3.3 VDD Supply voltage Core VDD Source power node Nonsource power node Supply voltage LREQ, CTL0, CTL1, D0-D7, LCLK VIH High-level input voltage MIN TYP (1) MAX 3.0 3.3 3.6 3.0 (2) 3.3 3.6 1.85 1.95 2.05 Low-level input voltage V V 2.6 LKON/DS2, PC0, PC1, PC2, PD, BMODE 0.7 × VDD RESETz 0.6 × VDD V LREQ, CTL0, CTL1, D0-D7, LCLK VIL UNIT 1.2 LKON/DS2, PC0, PC1, PC2, PD, BMODE 0.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com ELECTRICAL CHARACTERISTICS Driver over recommended ranges of operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN 56 Ω, See Figure 1 TYP MAX UNIT 172 265 mV (1) (1) mA VOD Differential output voltage IDIFF Drivers enabled, speed signaling Driver difference current, TPA+, TPA–, TPB+, TPB– off –1.05 ISP200 Common-mode speed signaling current, TPB+, TPB– S200 speed signaling enabled –4.84 (2) –2.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 Electrical Characteristics (continued) Thermal Characteristics TEST CONDITIONS (1) PARAMETER TYP TYP PFP ZAJ Package Package UNIT qja Junction-to-free-air thermal resistance Low K JEDEC Test Board, 1s (single signal layer), no air flow qja Junction-to-free-air thermal resistance High K JEDEC Test Board 2s2p (double signal layer, double buried power plane) qjc Junction-to-case-thermal resistance Cu Cold Plate Measurement Process 21.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION TPAx+ TPBx+ 56 Ω TPAx− TPBx− Figure 1. Test Load Diagram xCLK tsu th Dx, CTLx, LREQ Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms xCLK td Dx, CTLx Figure 3.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 APPLICATION INFORMATION Please obtain from the TI website or your local TI representative the reference schematics, reference layouts, debug documents, and software recommendations for the TSB81BA3E. Internal Register Configuration There are 16 accessible internal registers in the TSB81BA3E.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com Table 2. Base Register Field Descriptions (continued) FIELD SIZE TYPE Num_Ports 4 Rd Number of ports. For the TSB81BA3E, this field indicates the number of ports implemented in the PHY. This field is 3. PHY_Speed 3 Rd PHY speed capability. For the TSB81BA3E, this field is no longer used. This field is 111b. Speeds for 1394b PHYs must be checked on a port-by-port basis. Rd PHY repeater data delay.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 Table 2. Base Register Field Descriptions (continued) FIELD STOI PEI SIZE TYPE DESCRIPTION 1 Rd/Wr State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus reset to occur). This bit is reset to 0 by hardware reset or by writing a 1 to this register bit.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com Table 4. Page 0 (Port Status) Register Field Descriptions FIELD SIZE TYPE DESCRIPTION TPA line state. This field indicates the instantaneous TPA line state of the selected port, encoded as follows: Code Astat 2 Rd Arb Value 11 Z 01 1 10 0 00 invalid Bstat 2 Rd TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as the Astat field. Ch 1 Rd Child/parent status.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 Table 4. Page 0 (Port Status) Register Field Descriptions (continued) FIELD SIZE TYPE DESCRIPTION Max_port_speed 3 Rd/Wr Max_port_speed The maximum speed at which a port is allowed to operate in Beta mode.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com Table 5. Page 1 (Vendor ID) Register Configuration BIT POSITION ADDRESS 0 1 2 3 0000 4 5 6 7 Compliance 0001 Reserved 0010 Vendor_ID0 0011 Vendor_ID1 0100 Vendor_ID2 0101 Product_ID0 0110 Product_ID1 0111 Product_ID2 Table 6. Page 1 (Vendor ID) Register Field Descriptions FIELD SIZE TYPE DESCRIPTION Compliance 8 Rd Compliance level.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 Table 9. Power-Class Descriptions PC0-PC2 DESCRIPTION 000 Node does not need power and does not repeat power 001 Node is self-powered and provides a minimum of 15 W to the bus. 010 Node is self-powered and provides a minimum of 30 W to the bus. 011 Node is self-powered and provides a minimum of 45 W to the bus. 100 Node can be powered from the bus and is using up to 3 W; no additional power is needed to enable the link.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com Outer Cable Shield 0.001 µF 0.01 µF 1 MΩ Chassis Ground Figure 5. Typical DC-Isolated Outer Shield Termination Outer Cable Shield Chassis Ground Figure 6. Non-DC-Isolated Outer Shield Termination 10 kΩ Link Power LPS Square-Wave Input LPS 10 kΩ Figure 7. Nonisolated Connection Variations for LPS PHY VDD 18 kΩ LPS Square-Wave Signal 0.033 mF 13 kΩ PHY GND Figure 8.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 Designing With PowerPAD™ Devices (PFP Package Only) The TSB81BA3E is housed in a high performance, thermally enhanced, 80-terminal PFP PowerPAD™ package. Use of the PowerPAD™ package does not require any special considerations except to note that the PowerPAD™, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com The TSB81BA3E also functions with a LLC that is compliant with the older 1394 standards. This interface is compatible with both the older Annex J interface specified in the IEEE Std 1394--1995 (with the exception of the Annex J isolation interfacing method) and the PHY-LLC interface specified in 1394a--2000. When using a LLC compliant with this interface, the BMODE input must be tied low.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must be able to compensate for this difference over the maximum packet length. Larger clock variations may cause resynchronization overflows or underflows, resulting in corrupted packet data.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 The D0-D7 terminals form a bidirectional data bus, which transfers status information, control information, or packet data between the devices. The TSB81BA3E supports S100, S200, and S400 data transfers over the D0-D7 data bus. In S100 operation, only the D0 and D1 terminals are used; in S200 operation, only the D0-D3 terminals are used; and in S400 operation, all D0-D7 terminals are used for data transfer.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com The length of the stream varies depending on the type of request as shown in Table 12. Table 12. Request Stream Bit Length REQUEST TYPE NUMBER OF BITS Bus request 7 or 8 Read register request 9 Write register request 17 Acceleration control request 6 Regardless of the type of request, a start bit of 1 is required at the beginning of the stream and a stop bit of 0 is required at the end of the stream.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 Table 16. Read Register Request BIT(s) 0 NAME DESCRIPTION Start bit Indicates the beginning of the transfer (always 1) 1-3 Request type A 100 indicates this is a read register request. 4-7 Address Identifies the address of the PHY register to be read 8 Stop bit Indicates the end of the transfer (always 0) For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 17. Table 17.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com The TSB81BA3E includes several arbitration acceleration enhancements, which allow the PHY to improve bus performance and throughput by reducing the number and length of interpacket gaps. These enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following acknowledge packets.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 SYSCLK CTL0, CTL1 00 00 01 (a) D0, D1 00 (b) S[0:1] S[14:15] 00 Figure 12. Status Transfer Timing The sequence of events for a status transfer is as follows: a. Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along with the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle).
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com SYSCLK 10 CTL0, CTL1 (a) D0–D7 00 (b) XX (e) FF (data-on) (c) (d) SPD d0 dn 00 NOTE A: SPD = Speed code, see NO TAG. d0–dn = Packet data A. SPD = Speed code, see Table 20 d0-dn = Packet data Figure 13. Normal Packet Reception Timing The sequence of events for a normal packet reception is as follows: a. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 Table 20. Receive Speed Codes (1) D0-D7 (1) DATA RATE 00XX XXXX S100 0100 XXXX S200 0101 0000 S400 11YY YYYY data-on indication X = Output as 0 by PHY, ignored by LLC. Y = Output as 1 by PHY, ignored by LLC. Transmit When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com SYSCLK (a) CTL0, CTL1 D0–D7 (b) 00 11 00 00 (c) (d) 00 (e)/(f) 01 00 10 d0, d1, . . . dn (g) 00/01 00 00/SP 00 00 00 Link Controls CTL and D PHY High-Impedance CTL and D Outputs NOTE A: SPD = Speed code, see NO TAG. d0–dn = Packet data A. SPD = Speed code, see Table 20 d0-dn = Packet data Figure 15. Normal Packet Transmission Timing The sequence of events for a normal packet transmission is as follows: a.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 SYSCLK (a) CTL0, CTL1 00 D0–D7 11 (b) 00 (c) 00 00 (d) 01 (e) 00 00 00 00 Link Controls CTL and D PHY High-Impedance CTL and D Outputs Figure 16. Cancelled/Null Packet Transmission The sequence of events for a cancelled/null packet transmission is as follows: a. Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link. b. Optional idle cycle.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com Table 21. LPS Timing Parameters (continued) SYMBOL DESCRIPTION tLPS_DISABLE Time for PHY to recognize LPS deasserted and disable the interface tRESTORE Time to permit optional isolation circuits to restore during an interface reset tCLK_ACTIVATE (3) Time for PCLK to be activated from reassertion of LPS MIN MAX UNIT 26.03 26.11 ms 15 23 (3) ms 60 ns 7.3 ms PHY not in low-power state PHY in low-power state 5.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 When the interface is disabled, the PHY enters a low-power state if none of its ports are active. (a) (c) (d) PCLK CTL0, CTL1 D0–D7 (b) LREQ LPS tLPS_RESET tLPS_DISABLE Figure 18. Interface Disable The sequence of events for disabling the PHY-LLC is as follows: a. Normal operation.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 ISO www.ti.com (high) 7 Cycles SYSCLK (b) (c) CTL0 (d) CTL1 D0–D7 LREQ (a) LPS tCLK_ACTIVATE Figure 19. Interface Initialization The sequence of events for initialization of the PHY-LLC is as follows: a. LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum tRESTORE time, the LLC causes the interface to be initialized and restored to normal operation by reasserting the LPS signal.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 TSB41BA3B LCLK_PMC PCLK CTL0–CTL1 Link-Layer Controller D0–D7 LREQ LPS S5_LKON PINT Figure 20. PHY-LLC Interface The LCLK terminal provides a clock signal to the PHY. The LLC derives this clock from the PCLK signal and is phase-locked to the PCLK signal. All LLC to PHY transfers are synchronous to LCLK. The PCLK terminal provides a 98.304-MHz interface system clock.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com Table 22. CTL Encoding When PHY Has Control of the Bus CTL0 CTL1 NAME DESCRIPTION 0 0 Idle No activity (this is the default mode) 0 1 Status Status information is being sent from the PHY to the LLC. 1 0 Receive An incoming packet is being sent from the PHY to the LLC. 1 1 Grant The LLC has been given control of the bus to send an outgoing packet. Table 23.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 Table 25. Request Type Encoding (continued) LR1-LR4 NAME DESCRIPTION 0100 Current Current request. The PHY arbitrates for the bus to send an asynchronous packet in the current fairness interval. 0101 Reserved Reserved 0110 Isoch_Req_Even Isochronous even request. The PHY arbitrates for the bus to send an isochronous packet in the even isochronous period. 0111 Isoch_Req_Odd Isochronous odd request.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com NOTE The TSB81BA3E accepts a bus request with an invalid speed code and processes the bus request normally. However, during packet transmission for such a request, the TSB81BA3E ignores any data presented by the LLC and transmits a null packet. For a read register request, the length of the LREQ bit stream is 10 bits as shown in Table 29. Table 29.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 Status Transfer A status transfer is initiated by the PHY when status information is to be transferred to the LLC. Two types of status transfers can occur: bus status transfer and PHY status transfer. Bus status transfers send the following status information: bus reset indications, subaction and arbitration reset gap indications, cycle start indications, and PHY interface reset indications.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 LR0 www.ti.com LR2 LR1 LR3 LR (n-2) LR (n-1) Each cell represents one clock sample period, and n is the number of bits in the request stream. Figure 23. PINT (PHY Interrupt) Stream Table 33. PHY Status Transfer Encoding PI[1:3] 000 NAME DESCRIPTION NUMBER OF BITS NOP No status indication 5 001 PHY_INTERRUPT Interrupt indication: configuration time-out, cable-power failure, port event interrupt, or arbitration state machine time-out.
TSB81BA3E www.ti.com SLLS783A – MAY 2009 – REVISED MAY 2010 The TSB81BA3E also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization, to the LLC. This packet it transferred to the LLC just as any other received self-ID packet. PCLK CTL0, CTL1 10 (a) D0–D7 00 (e) (b) XX FF (data-on) (c) (d) SPD d0 dn 00 NOTE A: SPD = speed code, see NO TAG. d0–dn = packet data A. SPD = speed code, see Table 35. d0-dn = packet data Figure 24.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com PCLK CTL0, CTL1 (a) D0–D7 XX 10 00 (b) (c) 00 FF (data-on) Figure 26. Null Packet Reception Timing The sequence of events for a null packet reception is as follows: a. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted.
TSB81BA3E www.ti.
TSB81BA3E SLLS783A – MAY 2009 – REVISED MAY 2010 www.ti.com Table 37. ink Request Speed Code Encoding During Packet Transmission D5D6 DATA RATE 00 S100 01 S200 10 S400 11 S800 Table 38. Link Request Format Encoding During Packet Transmission D0 FORMAT 0 Link does not request either Beta or legacy packet format for bus transmission. 1 Link requests Beta packet format for bus transmission. Table 39.
TSB81BA3E www.ti.
PACKAGE OPTION ADDENDUM www.ti.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
