Datasheet

TSB81BA3D, TSB81BA3DI
IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
SLLS559E − DECEMBER 2002 − REVISED JUNE 2006
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394B INTERFACE)
receive (continued)
NOTE A: SPD = Speed code, see Table 35. d0–dn = Packet data. STATUS = status bits, see Table 32.
00
0010
XX dnd0SPD
(a) (b)
FF (data-on)D0–D7
CTL0, CTL1
PCLK
(c) (d)
(e)
01
STATUS
10
FF
(data-on)
Figure 25. Normal Packet Reception Timing with Optional Bus Status Transfer
The sequence of events for a normal packet reception is as follows:
(a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.
Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a
status transfer operation that is in progress so that the CTL lines may change from status to receive without
an intervening idle.
(b) Data-on indication. The PHY may assert the data-on indication code on the D lines for one or more cycles
preceding the speed-code. The PHY may optionally send a bus status transfer during the data-on indication
for one PCLK cycle. During this cycle, the PHY asserts status (01b) on the CTL lines while sending status
information on the D lines.
(c) Speed-code. The PHY indicates the speed of the received packet by asserting a speed-code on the D lines
for one cycle immediately preceding packet data. The link decodes the speed-code on the first receive cycle
for which the D lines are not the data-on code. If the speed-code is invalid or indicates a speed higher that
that which the link is capable of handling, then the link must ignore the subsequent data.
(d) Receive data. Following the data-on indication (if any) and the speed-code, the PHY asserts packet data
on the D lines with receive on the CTL lines for the remainder of the receive operation.
(e) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.
The PHY asserts at least one idle cycle following a receive operation.
00
0010
XX
(a)
(b) (c)
FF (data-on)D0–D7
CTL0, CTL1
PCLK
Figure 26. Null Packet Reception Timing