Datasheet

TSB81BA3D, TSB81BA3DI
IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
SLLS559E − DECEMBER 2002 − REVISED JUNE 2006
48
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394B INTERFACE)
status transfer (continued)
PHY status transfers use the PINT terminal to serially send status information to the LLC as shown in Figure 23.
PHY status transfers (Table 33) can occur at any time during normal operation. The PHY uses the
PHY_INTERRUPT PHY status transfer when required to interrupt the LLC due to a configuration timeout, a
cable power failure, a port interrupt, or an arbitration timeout. When transferring PHY register contents, the PHY
uses either the solicited or the unsolicited register read status transfer. The unsolicited register 0 contents are
passed to the LLC only during initialization of the serial bus. After any PHY-link interface initialization, the PHY
sends a PHY status transfer indicating whether or not a bus reset occurred during the inactive period of the
PHY-link interface. If the PHY receives an illegal request from the LLC, then the PHY issues an
INTERFACE_ERROR PHY status transfer.
Each cell represents one clock sample time, and n is the number of bits in the request stream.
LR1 LR2 LR3 LR (n-2)LR0 LR (n-1)
Figure 23. PINT (PHY Interrupt) Stream
Table 33. PHY Status Transfer Encoding
PI[1:3] NAME DESCRIPTION NUMBER OF BITS
000 NOP No status indication 5
001 PHY_INTERRUPT Interrupt indication: configuration timeout, cable power failure, port event
interrupt, or arbitration state machine timeout
5
010 PHY_REGISTER_SOL Solicited PHY register read 17
011 PHY_REGISTER_UNSOL Unsolicited PHY register read 17
100 PH_RESTORE_NO_RESET PHY-link interface initialized; no bus resets occurred 5
101 PH_RESTORE_RESET PHY-link interface initialized; a bus reset occurred 5
110 INTERFACE_ERROR PHY received illegal request 5
111 Reserved Reserved Reserved
Most PHY status transfers are 5 bits long. The transfer consists of a start bit (always 1), followed by a request
type (see Table 33), and lastly followed by a stop bit (always 0). The only exception is when the transfer of a
register contents occurs. Solicited and unsolicited PHY register read transfers are 17 bits long and include the
additional information of the register address and the data contents of the register (see Table 34).
Table 34. Register Read (Solicited and Unsolicited) PHY Status Transfer Encoding
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1−3 Request type A 010 or a 011 indicates a solicited or unsolicited register contents transfer
4−7 Address Identifies the address of the PHY register whose contents are being transferred
8−15 Data The contents of the register specified in bits 4 through 7
16 Stop bit Indicates the end of the transfer (always 0)