Datasheet

TSB81BA3D, TSB81BA3DI

IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS559E − DECEMBER 2002 − REVISED JUNE 2006

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394B INTERFACE)

status transfer

A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. Two types

of status transfers may occur: bus status transfer and PHY status transfer. Bus status transfers send the

following status information: bus reset indications, subaction and arbitration reset gap indications, cycle start

indications, and PHY interface reset indications. PHY status transfers send the following information: PHY

interrupt indications, unsolicited and solicited PHY register data, bus initialization indications, and PHY-link

interface error indications. The PHY uses a different mechanism to send the bus status transfer and the PHY

status transfer.

Bus status transfers use the CTL0−CTL1 and D0−D7 terminals to transfer status information. Bus status trans-

fers can occur during idle periods on the PHY-link interface or during packet reception. When the status transfer

occurs, a single PCLK cycle of status information is sent to the LLC. The information is sent such that each indi-

vidual Dn terminal conveys a different bus status transfer event. During any bus status transfer, only one status

bit is set. If the PHY-link interface is inactive, then the status information is not sent. When a bus reset on the

serial bus occurs, the PHY sends a bus reset indication (via the CTLn and Dn terminals), cancels all packet

transfer requests, sets asynchronous and isochronous phases to even, forwards self-ID packets to the link, and

sends an unsolicited PHY register 0 status transfer (via the PINT terminal) to the LLC. In the case of a PHY

interface reset operation, the PHY-link interface is reset on the following PCLK cycle.

Table 32 shows the definition of the bits during the bus status transfer and Figure 22 shows the timing.

Table 32. Status Bits

STATUS BIT DESCRIPTION

D0 Bus Reset

D1 Arbitration Reset Gap—Odd

D2 Arbitration Reset Gap—Even

D3 Cycle Start—Odd

D4 Cycle Start—Even

D5 Subaction Gap

D6 PHY Interface Reset

D7 Reserved

D[0:7]

XX ST XX

CTL[0:1]

XX 01 XX

Status Bits

Figure 22. Bus Status Transfer Timing