Datasheet

TSB81BA3D, TSB81BA3DI
IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
SLLS559E − DECEMBER 2002 − REVISED JUNE 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394B INTERFACE)
LLC service request (continued)
Table 24. Request Stream Bit Length
REQUEST TYPE NUMBER OF BITS
Bus request 11
Read register request 10
Write register request 18
Link notification request 6
PHY-link interface reset request 6
Regardless of the type of request, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0
is required at the end of the stream. The second through fifth bits of the request stream indicate the type of the
request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit stream.
The LREQ terminal is normally low.
Table 25 show the encoding for the request type.
Table 25. Request Type Encoding
LR1−LR4 NAME DESCRIPTION
0000 Reserved Reserved
0001 Immed_Req Immediate request. Upon detection of idle, the PHY arbitrates for the bus.
0010 Next_Even Next even request. The PHY arbitrates for the bus to send an asynchronous packet in the even fairness
interval phase.
0011 Next_Odd Next odd request. The PHY arbitrates for the bus to send an asynchronous packet in the odd fairness
interval phase.
0100 Current Current request. The PHY arbitrates for the bus to send an asynchronous packet in the current fairness
interval.
0101 Reserved Reserved
0110 Isoch_Req_Even Isochronous even request. The PHY arbitrates for the bus to send an isochronous packet in the even
isochronous period.
0111 Isoch_Req_Odd Isochronous odd request. The PHY arbitrates for the bus to send an isochronous packet in the odd
isochronous period.
1000 Cyc_Start_Req Cycle start request. The PHY arbitrates for the bus to send a cycle start packet.
1001 Reserved Reserved
1010 Reg_Read Register read request. The PHY returns the specified register contents through a status transfer.
1011 Reg_Write Register write request. Write to the specified register in the PHY.
1100 Isoch_Phase_Even Isochronous phase even notification. The link reports to the PHY that:
1) A cycle start packet has been received
2) The link has set the isochronous phase to even.
1101 Isoch_Phase_Odd Isochronous phase odd notification. The link reports to the PHY that:
1) A cycle start packet has been received
2) The link has set the isochronous phase to odd.
1110 Cycle_Start_Due Cycle start due notification. The link reports to the PHY that a cycle start packet is due for reception.
1111 Reserved Reserved
For a bus request, the length of the LREQ bit stream is 11 bits as shown in Table 26.