Datasheet

TSB81BA3D, TSB81BA3DI
IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
SLLS559E − DECEMBER 2002 − REVISED JUNE 2006
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394B INTERFACE)
The TSB81BA3D is designed to operate with a LLC such as the Texas Instruments TSB82AA2 when the
BMODE terminal is tied high. Details of operation for the Texas Instruments LLC devices are found in the
respective LLC data sheets. The following paragraphs describe the operation of the PHY-LLC interface. This
interface is formally specified in the IEEE P1394b standard.
The interface to the LLC consists of the PCLK, LCLK, CTL0−CTL1, D0−D7, LREQ, PINT, LPS, and LKON/DS2
terminals on the TSB81BA3D, as shown in Figure 20.
LKON/DS2
LPS
PCLK
LREQ
D0–D7
CTL0–CTL1
Link-Layer
Controller
TSB81AB3C
LCLK
PINT
Figure 20. PHY-LLC Interface
The LCLK terminal provides a clock signal to the PHY. The LLC derives this clock from the PCLK signal and
is phase-locked to the PCLK signal. All LLC to PHY transfers are synchronous to LCLK.
The PCLK terminal provides a 98.304-MHz interface system clock. All control, data, and PHY interrupt signals
are synchronized to the rising edge of PCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data
between the TSB81BA3D and LLC.
The D0−D7 terminals form a bidirectional data bus, which transfers status information, control information, or
packet data between the devices. The TSB81BA3D supports S400B and S800 data transfers over the D0−D7
data bus. In S400B and S800 operation all Dn terminals are used.
The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access
to the serial-bus for packet transmission, read or write PHY registers, or control arbitration acceleration. All data
on LREQ is synchronous to LCLK
The LPS and LKON/DS2 terminals are used for power management of the PHY and LLC. The LPS terminal
indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable PCLK. The
LKON/DS2 terminal sends a wake-up notification to the LLC and indicates an interrupt to the LLC when either
LPS is inactive or the PHY register L bit is 0.
The PINT terminal is used by the PHY for the serial transfer of status, interrupt, and other information to the LLC.