Datasheet

TSB81BA3D, TSB81BA3DI
IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
SLLS559E − DECEMBER 2002 − REVISED JUNE 2006
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394a−2000 INTERFACE)
interface reset and disable (continued)
PCLK
(a) (c)
(b)
CTL0, CTL1
D0 − D7
LREQ
LPS
T
LPS_RESET
(d)
T
LPS_DISABLE
Figure 18. Interface Disable
The sequence of events for disabling the PHY-LLC is as follows:
(a) Normal operation. Interface is operating normally, with LPS active, PCLK active, status and packet data
reception and transmission via the CTL and D lines, and request activity via the LREQ line.
(b) LPS deasserted. The LLC deasserts the LPS signal and, within 1.0 μs, terminates any request or interface
bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.
(c) Interface reset. After T
LPS_RESET
time, the PHY determines that LPS is inactive, terminates any interface
bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.
(d) Interface disabled. If the LPS signal remains inactive for T
LPS_DISABLE
time, then the PHY terminates PCLK
activity by driving the PCLK output low. The PHY-LLC interface is now in the disabled state.
After the interface has been reset, or reset and then disabled, the interface is initialized and restored to normal
operation when LPS is reasserted by the LLC. Figure 19 shows the timing for interface initialization.