Datasheet

TSB81BA3D, TSB81BA3DI
IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
SLLS559E − DECEMBER 2002 − REVISED JUNE 2006
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION (1394a−2000 INTERFACE)
status transfer (continued)
The sequence of events for a status transfer is as follows:
(a) Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along with
the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle). Normally (unless
interrupted by a receive operation), a status transfer is either 2 or 8 cycles long. A 2-cycle (4-bit) transfer
occurs when only status information is to be sent. An 8-cycle (16-bit) transfer occurs when register data is
to be sent in addition to any status information.
(b) Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines.
The PHY may also interrupt a status transfer at any cycle by asserting receive on the CTL lines to begin
a receive operation. The PHY asserts at least one idle cycle between consecutive status transfers.
receive
Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting
receive on the CTL terminals and a logic 1 on each of the D bus terminals (data-on indication). The PHY
indicates the start of a packet by placing the speed code (encoded as shown in Table 20) on the D terminals,
followed by packet data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet
has been transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All
received packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is
not included in the calculation of CRC or any other data protection mechanisms.
It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed
by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds
the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any
data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D
bus terminals, followed by Idle on the CTL terminals, without any speed code or data being transferred. In all
cases, in normal operation, the TSB81BA3D sends at least one data-on indication before sending the speed
code or terminating the receive operation.
The TSB81BA3D also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization,
to the LLC. This packet it transferred to the LLC just as any other received self-ID packet.
00
0010
XX dnd0SPD
(a)
(b)
FF (data-on)
D0–D7
CTL0, CTL1
SYSCLK
(c) (d)
(e)
NOTE A: SPD = Speed code, see Table 20. d0–dn = Packet data
Figure 13. Normal Packet Reception Timing