Datasheet

TSB81BA3D, TSB81BA3DI

IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS559E − DECEMBER 2002 − REVISED JUNE 2006

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

bus reset

It is recommended, that whenever the user has a choice, the user should initiate a bus reset by writing to the

initiate short bus reset (ISBR) bit (bit 1 PHY register 0101b). Care must be taken to not change the value of any

of the other writeable bits in this register when the ISBR bit is written to.

In the TSB81BA3D, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and initialization

sequence, however, it is recommended to use the ISBR bit instead. The IBR bit is located in PHY register 1 along

with the root-holdoff (RHB) bit and gap-count register. As required by the 1394b Supplement this configuration

maintains compatibility with older TI PHY designs which were based upon either the suggested register set

defined in Annex J of IEEE Std 1394−1995 or the 1394a−2000 Supplement. Therefore, whenever the IBR bit

is written, the RHB bit and gap-count are also necessarily written.

It is recommended that the RHB bit and gap-count only be updated by PHY configuration packets. The

TSB81BA3D is 1394a and 1394b compliant, and therefore both the reception and transmission of PHY

configuration packets cause the RHB and gap-count to be loaded, unlike older IEEE Std 1394−1995 compliant

PHYs which decode only received PHY configuration packets.

The gap-count is set to the maximum value of 63 after two consecutive bus resets without an intervening write

to the gap-count, either by a write to PHY register 1 or by a PHY configuration packet. This mechanism allows

a PHY configuration packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the

bus have updated their RHB bits and gap-count values, without having the gap-count set back to 63 by the bus

reset. The subsequent connection of a new node to the bus, which initiates a bus reset, then causes the

gap-count of each node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a

write to register 1 to set the IBR bit, then all other nodes on the bus have their gap-count values set to 63, while

this node’s gap-count remains set to the value just loaded by the write to PHY register 1.

Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use

of the IBR bit, RHB bit, and gap-count in PHY register 1:

D Following the transmission of a PHY configuration packet, a bus reset must be initiated in order to verify

that all nodes have correctly updated their RHB bits and gap-count values, and to ensure that a subsequent

new connection to the bus causes the gap-count to be set to 63 on all nodes in the bus. If this bus reset is

initiated by setting the IBR bit to 1, then the RHB bit and gap-count register must also be loaded with the

correct values consistent with the just transmitted PHY configuration packet. In the TSB81BA3D, the RHB

bit and gap-count have been updated to their correct values upon the transmission of the PHY configuration

packet, and so these values may first be read from register 1 and then rewritten.

D Other than to initiate the bus reset which must follow the transmission of a PHY configuration packet,

whenever the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to 63

so as to be consistent with other nodes on the bus, and the RHB bit must be maintained with its current value.

D The PHY register 1 must not be written to except to set the IBR bit. The RHB bit and gap-count must not

be written without also setting the IBR bit to 1.

D To avoid these problems all bus resets initiated by software must be initiated by writing the ISBR bit (bit 1

PHY register 0101b). Care must be taken to not change the value of any of the other writeable bits in this

be by means of the PHY configuration packet, which changes all nodes to the same gap count.