Datasheet

62
Table 62. Serial EEPROM Map
EEPROM
BYTE
ADDRESS
BYTE DESCRIPTION
00 PCI maximum latency (0h) PCI_minimum grant (0h)
01 PCI vendor ID
02 PCI vendor ID (msbyte)
03 PCI subsystem ID (lsbyte)
04 PCI subsystem ID (msbyte)
05
[7]
Link_enhancement
Control.enab_unfair
[6]
HCControl.
ProgramPhy
Enable
[53]
RSVD
[2]
RSVD
[1]
Link_enhancement
Control.enab_accel
[0]
RSVD
06
[76]
RSVD
Mini
ROM
address
[43]
RSVD
07 GUID high (lsbyte 0)
08 GUID high (byte 1)
09 GUID high (byte 2)
0A GUID high (msbyte 3)
0B GUID low (lsbyte 0)
0C GUID low (byte 1)
0D GUID low (byte 2)
0E GUID low (msbyte 3)
0F Checksum
10
[15]
dis_at_pipeline
[14]
RSVD
[1312]
ATX threshold
[118]
RSVD
11
§
[75]
RSVD
[4]
Disable
Target
Abort
[30]
RSVD
12
[15]
PME D3 Cold
[148]
RSVD
13
[70]
RSVD
14
[70]
RSVD
15 RSVD
16
[7]
CNA OUT Enable
[64]
RSVD
[3]
RSVD
[20]
RSVD
171F RSVD
Bit 2 at EEPROM byte offset 05h must be programmed to 0b.
Bit 14 must be programmed to 0 for normal operation.
§
Bits 20 at EEPROM byte offset 11h must be programmed to 000b to ensure proper functioning. By default, unprogrammed EEPROM bits are
1.
Bits 64 and 20 at EEPROM byte offset 16h must be programmed to 0 to ensure proper functioning. Bit 3 must be programmed to 1. If CNA
functionality is desired on terminal 96, bit 7 must be programmed to 1; otherwise, bit 7 can be programmed to 0.