Datasheet

61
6 Serial EEPROM Interface
The TSB43AB23 device provides a serial bus interface to initialize the GUID registers and a few PCI configuration
registers through a serial EEPROM. The TSB43AB23 device communicates with the serial EEPROM via the 2-wire
serial interface.
After power up the serial interface initializes the locations listed in Table 61. While the TSB43AB23 device accesses
the serial EEPROM, all incoming PCI slave accesses are terminated with retry status. Table 62 shows the serial
EEPROM memory map required for initializing the TSB43AB23 registers.
NOTE: If an EEPROM is implemented in the design, byte offsets 00h16h must be
programmed. An unprogrammed EEPROM defaults to all 1s, which can adversely impact
device operation.
Table 61. Registers and Bits Loadable Through Serial EEPROM
EEPROM BYTE OFFSET
OHCI/PCI
CONFIGURATION
OFFSET
REGISTER NAME
REGISTER BITS
LOADED
FROM EEPROM
00h PCI register (3Eh) PCI maximum latency, PCI minimum grant 150
01h PCI register (2Dh) Vendor identification 150
03h PCI register (2Ch) Subsystem identification 150
05h (bit 6) OHCI register (50h) Host controller control 23
05h PCI register (F4h) Link enhancement control 7, 6, 1
06h OHCI register (04h) GUID ROM 70
07h0Ah OHCI register (24h) GUID high 310
0Bh0Eh OHCI register (28h) GUID low 310
10h PCI register (F4h) Link enhancement control 1512
11h12h PCI register (F0h) Miscellaneous configuration
15, 4
16h PCI register (ECh) PCI PHY control
70
Bits 20 at EEPROM byte offset 11h must be programmed to 000b to ensure proper functioning. By default, unprogrammed EEPROM
bits are 1.
Bits 64 and 20 at EEPROM byte offset 16h must be programmed to 0 to ensure proper functioning. Bit 3 must be programmed to 1.
If CNA functionality is desired on terminal 96, bit 7 must be programmed to 1; otherwise, bit 7 can be programmed to 0.