Datasheet

vii
List of Tables
Table Title Page
2–1 PDT Package Signals Sorted by Terminal Number 2–4. . . . . . . . . . . . . . . . . .
2–2 PGE Package Signals Sorted by Terminal Number 2–5. . . . . . . . . . . . . . . . . .
2–3 Signal Names Sorted Alphanumerically to Terminal Number 2–6. . . . . . . . . .
2–4 PCI System Terminals 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 PCI Address and Data Terminals 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 PCI Interface Control Terminals 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 Miscellaneous Terminals 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Physical Layer Terminals 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 Power Supply Terminals 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Bit Field Access Tag Descriptions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 PCI Configuration Register Map 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Command Register Description 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 Status Register Description 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Class Code and Revision ID Register Description 3–6. . . . . . . . . . . . . . . . . . .
3–6 Latency Timer and Class Cache Line Size Register Description 3–6. . . . . . .
3–7 Header Type and BIST Register Description 3–7. . . . . . . . . . . . . . . . . . . . . . . .
3–8 OHCI Base Address Register Description 3–7. . . . . . . . . . . . . . . . . . . . . . . . . .
3–9 TI Base Address Register Description 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–10 Subsystem Identification Register Description 3–9. . . . . . . . . . . . . . . . . . . . . .
3–11 Interrupt Line and Pin Registers Description 3–10. . . . . . . . . . . . . . . . . . . . . . . .
3–12 MIN_GNT and MAX_LAT Register Description 3–10. . . . . . . . . . . . . . . . . . . . .
3–13 OHCI Control Register Description 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–14 Capability ID and Next Item Pointer Registers Description 3–11. . . . . . . . . . . .
3–15 Power Management Capabilities Register Description 3–12. . . . . . . . . . . . . . .
3–16 Power Management Control and Status Register Description 3–13. . . . . . . . .
3–17 Power Management Extension Registers Description 3–13. . . . . . . . . . . . . . . .
3–18 PCI PHY Control Register 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–19 Miscellaneous Configuration Register 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–20 Link Enhancement Control Register Description 3–16. . . . . . . . . . . . . . . . . . . .
3–21 Subsystem Access Register Description 3–17. . . . . . . . . . . . . . . . . . . . . . . . . . .
3–22 General-Purpose Input/Output Control Register Description 3–18. . . . . . . . . .
4–1 OHCI Register Map 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 OHCI Version Register Description 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 GUID ROM Register Description 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Asynchronous Transmit Retries Register Description 4–6. . . . . . . . . . . . . . . .
4–5 CSR Control Register Description 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 Configuration ROM Header Register Description 4–8. . . . . . . . . . . . . . . . . . . .