Datasheet

314
3.20 PCI PHY Control Register
The PCI PHY control register provides a method for enabling the PHY CNA output. See Table 318 for a complete
description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PCI PHY control
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PCI PHY control
Type R R R R R R R R R/W R R R R/W R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Register: PCI PHY control
Offset: ECh
Type: Read/Write, read-only
Default: 0000 0008h
Table 318. PCI PHY Control Register
BIT FIELD NAME TYPE DESCRIPTION
318 RSVD R Reserved. Bits 318 return 0s when read.
7 CNAOUT R/W When bit 7 is set to 1, the PHY CNA output is routed to terminal 96. When implementing a serial
EEPROM, this bit can be set by programming bit 7 of offset 16h in the EEPROM to 1.
64 RSVD R Reserved. Bits 64 return 0s when read. These bits are affected when implementing a serial
EEPROM; thus, bits 64 at EEPROM byte offset 16h must be programmed to 0.
3 RSVD R Reserved. Bit 3 defaults to 1 to indicate compliance with IEEE Std 1394a-2000. If a serial
EEPROM is implemented, bit 3 at EEPROM byte offset 16h must be set to 1. See Table 62,
Serial EEPROM Map.
20 RSVD R Reserved. Bits 20 return 0s when read. These bits are affected when implementing a serial
EEPROM; thus, bits 20 at EEPROM byte offset 16h must be programmed to 0.