Datasheet
3–13
3.18 Power Management Control and Status Register
The power management control and status register implements the control and status of the PCI power management
function. This register is not affected by the internally generated reset caused by the transition from the D3
hot
to D0
state. See Table 3–16 for a complete description of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Power management control and status
Type RWC R R R R R R R/W R R R R R R R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Power management control and status
Offset: 48h
Type: Read/Clear, Read/Write, Read-only
Default: 0000h
Table 3–16. Power Management Control and Status Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 PME_STS RWC Bit 15 is set to 1 when the TSB43AB23 device normally asserts the PCI_PME signal independent of
the state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, which also clears the PCI_PME
signal driven by the TSB43AB23 device. Writing a 0 to this bit has no effect.
14–13 DATA_SCALE R This field returns 0s, because the data register is not implemented.
12–9 DATA_SELECT R This field returns 0s, because the data register is not implemented.
8 PME_ENB R/W When bit 8 is set to 1, PME assertion is enabled. When bit 8 is cleared, PME assertion is disabled. This
bit defaults to 0 if the function does not support PME
generation from D3
cold
. If the function supports
PME
from D3
cold
, this bit is sticky and must be explicitly cleared by the operating system each time
it is initially loaded.
7–2 RSVD R Reserved. Bits 7–2 return 0s when read.
1–0 PWR_STATE R/W Power state. This 2-bit field sets the TSB43AB23 device power state and is encoded as follows:
00 = Current power state is D0.
01 = Current power state is D1.
10 = Current power state is D2.
11 = Current power state is D3.
3.19 Power Management Extension Registers
The power management extension register provides extended power-management features not applicable to the
TSB43AB23 device; thus, it is read-only and returns 0 when read. See Table 3–17 for a complete description of the
register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Power management extension
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Power management extension
Offset: 4Ah
Type: Read-only
Default: 0000h
Table 3–17. Power Management Extension Registers Description
BIT FIELD NAME TYPE DESCRIPTION
15–0 RSVD R Reserved. Bits 15–0 return 0s when read.