Datasheet

3–12
3.17 Power Management Capabilities Register
The power management capabilities register indicates the capabilities of the TSB43AB23 device related to PCI power
management. See Table 3–15 for a complete description of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Power management capabilities
Type RU R R R R R R R R R R R R R R R
Default 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0
Register: Power management capabilities
Offset: 46h
Type: Read/Update, Read-only
Default: 7E02h
Table 3–15. Power Management Capabilities Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 PME_D3COLD RU PCI_PME support from D3
cold
. This bit can be set to 1 or cleared to 0 via bit 15 (PME_D3COLD) in
the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.21,
Miscellaneous Configuration Register). The miscellaneous configuration register is loaded from ROM.
When this bit is set to 1, it indicates that the TSB43AB23 device is capable of generating a PCI_PME
wake event from D3
cold
. This bit state is dependent upon the TSB43AB23 V
AUX
implementation and
may be configured by using bit 15 (PME_D3COLD) in the miscellaneous configuration register (see
Section 3.21).
14–11 PME_SUPPORT R PCI_PME support. This 4-bit field indicates the power states from which the TSB43AB23 device may
assert PCI_PME
. This field returns a value of 1111b by default, indicating that PCI_PME may be
asserted from the D3
hot
, D2, D1, and D0 power states.
10 D2_SUPPORT R D2 support. Bit 10 is hardwired to 1, indicating that the TSB43AB23 device supports the D2 power
state.
9 D1_SUPPORT R D1 support. Bit 9 is hardwired to 1, indicating that the TSB43AB23 device supports the D1 power state.
8–6 AUX_CURRENT R Auxiliary current. This 3-bit field reports the 3.3-V
AUX
auxiliary current requirements. When bit 15
(PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b.
000b = Self-powered
001b = 55 mA (3.3-V
AUX
maximum current required)
5 DSI R Device-specific initialization. This bit returns 0 when read, indicating that the TSB43AB23 device does
not require special initialization beyond the standard PCI configuration header before a generic class
driver is able to use it.
4 RSVD R Reserved. Bit 4 returns 0 when read.
3 PME_CLK R PCI_PME clock. This bit returns 0 when read, indicating that no host bus clock is required for the
TSB43AB23 device to generate PCI_PME
.
2–0 PM_VERSION R Power-management version. This field returns 010b when read, indicating that the TSB43AB23 device
is compatible with the registers described in the PCI Bus Power Management Interface Specification
(Revision 1.1).