Datasheet
3–5
3.5 Status Register
The status register provides status over the TSB43AB23 interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 3–4 for a complete
description of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Status
Type RCU RCU RCU RCU RCU R R RCU R R R R R R R R
Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0
Register: Status
Offset: 06h
Type: Read/Clear/Update, Read-only
Default: 0210h
Table 3–4. Status Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 PAR_ERR RCU Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected.
14 SYS_ERR RCU Signaled system error. Bit 14 is set to 1 when PCI_SERR is enabled and the TSB43AB23 device has
signaled a system error to the host.
13 MABORT RCU Received master abort. Bit 13 is set to 1 when a cycle initiated by the TSB43AB23 device on the PCI
bus has been terminated by a master abort.
12 TABORT_REC RCU Received target abort. Bit 12 is set to 1 when a cycle initiated by the TSB43AB23 device on the PCI
bus was terminated by a target abort.
11 TABORT_SIG RCU Signaled target abort. Bit 11 is set to 1 by the TSB43AB23 device when it terminates a transaction on
the PCI bus with a target abort.
10–9 PCI_SPEED R DEVSEL timing. Bits 10 and 9 encode the timing of PCI_DEVSEL and are hardwired to 01b, indicating
that the TSB43AB23 device asserts this signal at a medium speed on nonconfiguration cycle
accesses.
8 DATAPAR RCU Data parity error detected. Bit 8 is set to 1 when the following conditions have been met:
a. PCI_PERR
was asserted by any PCI device including the TSB43AB23 device.
b. The TSB43AB23 device was the bus master during the data parity error.
c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space
(see Section 3.4, Command Register) is set to 1.
7 FBB_CAP R Fast back-to-back capable. The TSB43AB23 device cannot accept fast back-to-back transactions;
therefore, bit 7 is hardwired to 0.
6 UDF R User-definable features (UDF) supported. The TSB43AB23 device does not support the UDF;
therefore, bit 6 is hardwired to 0.
5 66MHZ R 66-MHz capable. The TSB43AB23 device operates at a maximum PCI_CLK frequency of 33 MHz;
therefore, bit 5 is hardwired to 0.
4 CAPLIST R Capabilities list. Bit 4 returns 1 when read, indicating that capabilities additional to standard PCI are
implemented. The linked list of PCI power-management capabilities is implemented in this function.
3–0 RSVD R Reserved. Bits 3–0 return 0s when read.