Datasheet

34
3.3 Device ID Register
The device ID register contains a value assigned to the TSB43AB23 device by Texas Instruments. The device
identification for the TSB43AB23 device is 8024h.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Device ID
Type R R R R R R R R R R R R R R R R
Default 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0
Register: Device ID
Offset: 02h
Type: Read-only
Default: 8024h
3.4 Command Register
The command register provides control over the TSB43AB23 interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 33 for a complete
description of the register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Command
Type R R R R R R R R/W R R/W R R/W R R/W R/W R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Command
Offset: 04h
Type: Read/Write, Read-only
Default: 0000h
Table 33. Command Register Description
BIT FIELD NAME TYPE DESCRIPTION
1510 RSVD R Reserved. Bits 1510 return 0s when read.
9 FBB_ENB R Fast back-to-back enable. The TSB43AB23 device does not generate fast back-to-back transactions;
therefore, bit 9 returns 0 when read.
8 SERR_ENB R/W PCI_SERR enable. When bit 8 is set to 1, the TSB43AB23 PCI_SERR driver is enabled. PCI_SERR
can be asserted after detecting an address parity error on the PCI bus.
7 STEP_ENB R Address/data stepping control. The TSB43AB23 device does not support address/data stepping;
therefore, bit 7 is hardwired to 0.
6 PERR_ENB R/W Parity error enable. When bit 6 is set to 1, the TSB43AB23 device is enabled to drive PCI_PERR
response to parity errors through the PCI_PERR signal.
5 VGA_ENB R VGA palette snoop enable. The TSB43AB23 device does not feature VGA palette snooping; therefore,
bit 5 returns 0 when read.
4 MWI_ENB R/W Memory write and invalidate enable. When bit 4 is set to 1, the TSB43AB23 device is enabled to
generate MWI PCI bus commands. If this bit is cleared, the TSB43AB23 device generates memory
write commands instead.
3 SPECIAL R Special cycle enable. The TSB43AB23 function does not respond to special cycle transactions;
therefore, bit 3 returns 0 when read.
2 MASTER_ENB R/W Bus master enable. When bit 2 is set to 1, the TSB43AB23 device is enabled to initiate cycles on the
PCI bus.
1 MEMORY_ENB R/W Memory response enable. Setting bit 1 to 1 enables the TSB43AB23 device to respond to memory
cycles on the PCI bus. This bit must be set to access OHCI registers.
0 IO_ENB R I/O space enable. The TSB43AB23 device does not implement any I/O-mapped functionality;
therefore, bit 0 returns 0 when read.