Datasheet
3–2
Received Data
Decoder/Retimer
Arbitration
and Control
State Machine
Logic
Bias Voltage
and
Current Generator
Transmit Data
Encoder
Cable Port 1
Crystal
Oscillator,
PLL System,
and Clock
Generator
Cable Port 2
Internal
Registers
Isochronous
Transmit
Contexts
Asynchronous
Transmit
Contexts
Physical DMA
and Response
PCI
Target
SM
PHY
Register
Access
and
Status
Monitor
Central
Arbiter
and
PCI
Initiator
SM
Cycle Start
Generator and
Cycle Monitor
Synthesized
Bus Reset
Receive
FIFO
Link
Transmit
Link
Receive
PCI
Host
Bus
Interface
Resp
Time-out
Request
Filters
General
Request Receive
Asynchronous
Response
Receive
Isochronous
Receive
Contexts
OHCI PCI Power
Mgmt and CLKRUN
Transmit
FIFO
Receive
Acknowledge
Serial
ROM
GPIOs
CRC
Misc
Interface
PHY/
Link
Interface
Cable Port 0
Figure 3–1. TSB43AB23 Block Diagram