Datasheet

211
Table 29. Power Supply Terminals
TERMINAL
NAME
PDT
NO.
PGE
NO.
TYPE I/O DESCRIPTION
AGND
71, 73, 76, 80,
84, 89, 97
81, 83, 86, 90,
94, 99, 111
Supply
Analog circuit ground terminals. These terminals must be tied together
to the low-impedance circuit board ground plane.
AV
DD
70, 72, 81, 85,
90, 93, 98
80, 82, 91, 95,
100, 103, 112
Supply
Analog circuit power terminals. A parallel combination of high
frequency decoupling capacitors near each terminal is suggested,
such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering
capacitors are also recommended. These supply terminals are
separated from PLLV
DD
and DV
DD
internal to the device to provide
noise isolation. They must be tied at a low-impedance point on the
circuit board.
DGND
1, 12, 23, 32,
36, 43, 51, 66,
113, 119
3, 14, 25, 34,
42, 49, 57, 76,
127, 133
Supply
Digital circuit ground terminals. These terminals must be tied together
to the low-impedance circuit board ground plane.
DV
DD
7, 19, 27, 40,
56, 65, 111,
123
9, 21, 29, 46,
62, 75, 125,
137
Supply
Digital circuit power terminals. A parallel combination of high frequency
decoupling capacitors near each DV
DD
terminal is suggested, such as
0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are
also recommended. These supply terminals are separated from
PLLV
DD
and AV
DD
internal to the device to provide noise isolation. They
must be tied at a low-impedance point on the circuit board.
PHY_TEST_MA 68 78
Test control input. This input is used in the manufacturing test of the
TSB43AB23 device. For normal use, the terminal must be tied to DV
DD
.
PLL
GND
104 118 Supply
PLL circuit ground terminal. This terminal must be tied to the
low-impedance circuit board ground plane.
PLLV
DD
103 117 Supply
PLL circuit power terminal. A parallel combination of high frequency
decoupling capacitors near the terminal is suggested, such as 0.1 µF
and 0.001 µF. Lower frequency 10-µF filtering capacitors are also
recommended. This supply terminal is separated from DV
DD
and AV
DD
internal to the device to provide noise isolation. It must be tied to a
low-impedance point on the circuit board.
REG18 61, 126 67, 140 Supply
REG18. 1.8-V power supply for the device core. The internal voltage
regulator provides 1.8 V from DV
DD
. When the internal regulator is
disabled (REG_EN
is high), the REG18 terminals can be used to supply
an external 1.8-V supply to the TSB43AB23 core. It is recommended
that 0.1-µF bypass capacitors be used and placed close to these
terminals.
V
DDP
3, 16, 30, 46,
116
5, 18, 32, 52,
130
Supply
PCI signaling clamp voltage power input. PCI signals are clamped per
the PCI Local Bus Specification. In addition, if a 5-V ROM is used, the
V
DDP
must be connected to 5 V.