Datasheet

29
Table 27. Miscellaneous Terminals
TERMINAL
NAME PDT
NO.
PGE
NO.
I/O DESCRIPTION
CYCLEIN 55 61 I/O
The CYCLEIN terminal allows an external 8-kHz clock to be used as a cycle timer for synchronization
with other system devices.
If this terminal is not implemented, it must be pulled high to DV
DD
through a pullup resistor.
CYCLEOUT 54 60 I/O
The CYCLEOUT terminal provides an 8-kHz cycle timer synchronization signal. If CYCLEOUT is not
implemented, this terminal must be pulled down to ground through a pulldown resistor.
REG_EN 107 121 I
Regulator enable. This terminal must be tied to ground to enable the internal voltage regulator. When
using a single 3.3-V supply, this terminal must be tied to ground to enable the internal voltage regulator.
When using a dual 1.8-V/3.3-V supply to provide power to the device, REG_EN must be pulled to DV
DD
to disable the internal voltage regulator.
GPIO2/TEST0 58 64 I/O
General-purpose I/O [2]. This terminal defaults as an input and if it is not implemented, it is
recommended that it be pulled low to ground with a 220- resistor.
GPIO3/TEST1 57 63 I/O
General-purpose I/O [3]. This terminal defaults as an input and if it is not implemented, it is
recommended that it be pulled low to ground with a 220- resistor.
SCL 59 65 I/O
Serial clock. This terminal provides the serial clock signaling and is implemented as open-drain. For
normal operation (a ROM is implemented in the design), this terminal must be pulled high to the ROM
DV
DD
with a 2.7-k resistor. Otherwise, it must be pulled low to ground with a 220- resistor.
SDA 60 66 I/O
Serial data. At PCI_RST, the SDA signal is sampled to determine if a two-wire serial ROM is present.
If the serial ROM is detected, this terminal provides the serial data signaling.
This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the
design), this terminal must be pulled high to the ROM DV
DD
with a 2.7-k resistor. Otherwise, it must
be pulled low to ground with a 220- resistor.