Datasheet

9–5
9.4.3 Receiver
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Z
Differential impedance
Drivers disabled
4 7 kΩ
Z
ID
Differential impedance Drivers disabled
4 pF
Z
Common mode impedance
Drivers disabled
20 kΩ
Z
IC
Common-mode impedance Drivers disabled
24 pF
V
TH-R
Receiver input threshold voltage Drivers disabled –30 30 mV
V
TH-CB
Cable bias detect threshold, TPBx cable inputs Drivers disabled 0.6 1.0 V
V
TH
+ Positive arbitration comparator threshold voltage Drivers disabled 89 168 mV
V
TH
– Negative arbitration comparator threshold voltage Drivers disabled –168 –89 mV
V
TH–SP200
Speed signal threshold
TPBIAS–TPA common mode
voltage, drivers disabled
49 131 mV
V
TH–SP400
Speed signal threshold
TPBIAS–TPA common mode
voltage, drivers disabled
314 396 mV
9.5 Thermal Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
128-PDT Rθ
JA,
high-K board 74.6 °C/W
128-PDT Rθ
JA,
low-K board
Board mounted, no air flow, JEDEC test board
101.3 °C/W
128-PDT Rθ
JC
,,
18.7 °C/W
9.6 Switching Characteristics for PHY Port Interface
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Jitter, transmit Between TPA and TPB ±0.15 ns
Skew, transmit Between TPA and TPB ±0.10 ns
t
r
TP differential rise time, transmit 10% to 90%, at 1394 connector 0.5 1.2 ns
t
f
TP differential fall time, transmit 90% to 10%, at 1394 connector 0.5 1.2 ns
9.7 Operating, Timing, and Switching Characteristics of XI
PARAMETER MIN TYP MAX UNIT
V
DD
3.0 3.3 3.6 V (PLLV
DD
)
V
IH
High-level input voltage 0.63V
DD
V
V
IL
Low-level input voltage 0.33V
DD
V
Input clock frequency 24.576 MHz
Input clock frequency tolerance <100 PPM
Input slew rate 0.2 4 V/ns
Input clock duty cycle 40% 60%
9.8 Switching Characteristics for PCI Interface
†
PARAMETER MEASURED MIN TYP MAX UNIT
t
su
Setup time before PCLK –50% to 50% 7 ns
t
h
Hold time before PCLK –50% to 50% 0 ns
t
val
Delay time, PCLK to data valid –50% to 50% 2 11 ns
†
These parameters are ensured by design.