Datasheet

92
9.2 Recommended Operating Conditions
TEST
CONDITION
MIN NOM MAX UNIT
REG18 1.6 1.8 2.0 V
Core voltage, AV
DD
3 3.3 3.6 V
Core voltage, DV
DD
3 3.3 3.6 V
Core voltage, PLLV
DD
2.7 3 3.6 V
Output voltage, V
O
TTL and LVCMOS terminals 0 DV
DD
V
PCI I/O clampin
g
volta
g
e,
V
DDP
= 3.3 V 3 3.3 3.6
V
PCI
I/O
clam ing
voltage
,
V
DDP
V
DDP
= 5 V 4.5 5 5.5
V
PCI
3.3 V 0.475V
DDP
V
DDP
PCI
5 V 2 V
DDP
High-level input voltage, V
IH
PC(02) 0.7DV
DD
DV
DD
V
High level
in ut
voltage,
V
IH
G_RST 0.6DV
DD
DV
DD
Miscellaneous
2 V
DDP
PCI 3.3 V 0 0.325V
DDP
PCI 5 V 0 0.8
Low-level input voltage, V
IL
PC(02) 0 0.2DV
DD
V
Low level
in ut
voltage,
V
IL
G_RST 0 0.3DV
DD
Miscellaneous
0 0.8
Input voltage V
PCI 3.3 V 0 V
DDP
V
Input voltage, V
I
Miscellaneous
0 V
DDP
V
Output voltage V
O
§
PCI 3.3 V 0 DV
DD
V
Output voltage, V
O
§
Miscellaneous
0 DV
DD
V
Input transition time
(t
r
and t
f
), t
t
PCI 0 6 ns
Operating free-air
temperature, T
A
Rθ
JA
= 70.82°C/W, T
A
= 70°C 99.3 °C
Output current, I
O
TPBIAS outputs 5.6 1.3 mA
Differential input voltage V
Cable inputs, during data reception 118 260
mV
Differential input voltage, V
ID
Cable inputs, during arbitration 168 265
mV
Common-mode input volta
g
e,
TPB cable inputs, source power node 0.4706 2.515
V
Common mode
in ut
voltage
,
V
IC
TPB cable inputs, nonsource power node 0.4706 2.015
V
Maximum junction
128-PDT high-K JEDEC board
Rθ
JA
= 74.6°C/W, T
A
= 70°C, Pd = 0.6 W
119.2
°C
Maximum
junction
temperature, T
J
128-PDT low-K JEDEC board
Rθ
JA
= 101.3°C/W, T
A
= 70°C, Pd = 0.6 W
136.9
°C
Power-up reset time, t
pu
G_RST input 2 ms
TPA, TPB cable inputs, S100 operation ±1.08
Receive input jitter
TPA, TPB cable inputs, S200 operation ±0.5
ns
Receive
in ut
jitter
TPA, TPB cable inputs, S400 operation ±0.315
ns
Applies to external inputs and bidirectional buffers without hysteresis.
Miscellaneous terminals are: GPIO2 (90), GPIO3 (89), SDA (92), SCL (91).
§
Applies to external output buffers.
For a node that does not source power; see Section 4.2.2.2 in IEEE Std 1394a-2000.