Datasheet
8–2
1 MΩ
0.001 µF
0.01 µF
Outer Cable Shield
Chassis Ground
Figure 8–2. Typical Compliant DC Isolated Outer Shield Termination
Outer Cable Shield
Chassis Ground
Figure 8–3. Non-DC Isolated Outer Shield Termination
8.2 Crystal Selection
The TSB43AB23 device is designed to use an external 24.576-MHz crystal connected between the XI and XO pins
to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the
various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates.
A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394-1995. Adjacent
PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHY devices
must be able to compensate for this difference over the maximum packet length. Large clock variations may cause
resynchronization overflows or underflows, resulting in corrupted packet data.
The following are some typical specifications for crystals used with the PHYs from TI in order to achieve the required
frequency accuracy and stability:
• Crystal mode of operation: Fundamental
• Frequency tolerance @ 25°C: Total frequency variation for the complete circuit is ±100 ppm. A crystal with
±30 ppm frequency tolerance is recommended for adequate margin.
• Frequency stability (over temperature and age): A crystal with ±30 ppm frequency stability is recommended
for adequate margin.
NOTE: The total frequency variation must be kept below ±100 ppm from nominal with some
allowance for error introduced by board and device variations. Trade-offs between frequency
tolerance and stability may be made as long as the total frequency variation is less than
±100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and
the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible
variation due to the crystal alone. Crystal aging also contributes to the frequency variation.
• Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent
upon the load capacitance specified for the crystal. Total load capacitance (C
L
) is a function of not only the
discrete load capacitors, but also board layout and circuit. It is recommended that load capacitors with a
maximum of ±5% tolerance be used.