Datasheet

vi
List of Illustrations
Figure Title Page
2–1 TSB43AB22A Terminal Assignments 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 TSB43AB22A Block Diagram 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–1 TP Cable Connections 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–2 Typical Compliant DC Isolated Outer Shield Termination 8–2. . . . . . . . . . . . .
8–3 Non-DC Isolated Outer Shield Termination 8–2. . . . . . . . . . . . . . . . . . . . . . . . .
8–4 Load Capacitance for the TSB43AB22A PHY 8–3. . . . . . . . . . . . . . . . . . . . . . .
8–5 Recommended Crystal and Capacitor Layout 8–3. . . . . . . . . . . . . . . . . . . . . . .
9–1 Test Load Diagram 9–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–2 CardBus PC Card Clock Waveform 9–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables
Table Title Page
2–1 Signals Sorted by Terminal Number 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Signal Names Sorted Alphanumerically to Terminal Number 2–3. . . . . . . . . .
2–3 PCI System Terminals 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 PCI Address and Data Terminals 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 PCI Interface Control Terminals 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Miscellaneous Terminals 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 Physical Layer Terminals 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Power Supply Terminals 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Bit Field Access Tag Descriptions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 PCI Configuration Register Map 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Command Register Description 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 Status Register Description 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Class Code and Revision ID Register Description 3–6. . . . . . . . . . . . . . . . . . .
3–6 Latency Timer and Class Cache Line Size Register Description 3–6. . . . . . .
3–7 Header Type and BIST Register Description 3–7. . . . . . . . . . . . . . . . . . . . . . . .
3–8 OHCI Base Address Register Description 3–7. . . . . . . . . . . . . . . . . . . . . . . . . .
3–9 TI Base Address Register Description 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–10 CardBus CIS Base Address Register Description 3–9. . . . . . . . . . . . . . . . . . .
3–11 CardBus CIS Pointer Register Description 3–10. . . . . . . . . . . . . . . . . . . . . . . . .
3–12 Subsystem Identification Register Description 3–11. . . . . . . . . . . . . . . . . . . . . .
3–13 Interrupt Line and Pin Registers Description 3–12. . . . . . . . . . . . . . . . . . . . . . . .