Datasheet
2–4
The terminals are grouped in tables by functionality, such as PCI system function and power supply function (see
Table 2–3 through Table 2–8). The terminal numbers are also listed for convenient reference.
Table 2–3. PCI System Terminals
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
G_RST 14 I
Global power reset. This reset brings all of the TSB43AB22A internal registers to their default states, including
those registers not reset by PCI_RST
. When G_RST is asserted, the device is completely nonfunctional,
placing all output buffers in a high impedance state.
When implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets
to the TSB43AB22A device. G_RST
is designed to be a one-time power-on reset, and PCI_RST must be
connected to the PCI bus RST
. G_RST must be asserted for a minimum of 2 ms.
PCI_CLK 16 I
PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising
edge of PCI_CLK.
PCI_INTA/CINT 13 O
Interrupt signal. This output indicates interrupts from the TSB43AB22A device to the host. This terminal signals
a CardBus interrupt (CINT
) when CARDBUS (terminal 86) is tied low.
PCI_RST 85 I
PCI reset. When this bus reset is asserted, the TSB43AB22A device places all output buffers in a
high-impedance state and resets all internal registers except device power management context- and
vendor-specific bits initialized by host power-on software. When PCI_RST is asserted, the device is
completely nonfunctional. Connect this terminal to PCI bus RST
.
Table 2–4. PCI Address and Data Terminals
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
22
24
25
26
28
29
31
32
37
38
40
41
42
43
45
46
61
63
65
66
67
69
70
71
74
76
77
79
80
81
82
84
I/O
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the PCI interface.
During the address phase of a PCI cycle, AD31–AD0 contain a 32-bit address or other destination information.
During the data phase, AD31–AD0 contain data.