Datasheet

9–6
9.8.1 CardBus PC Card Clock Specifications
PARAMETER MIN MAX UNIT
t
cyc
CCLK cycle time (see Note 7) 30 R ns
t
high
CCLK high time 12 ns
t
low
CCLK low time 12 ns
–
CCLK slew rate (see Note 8) 1 4 V/ns
NOTES: 7. In general, all CardBus PC Card components must work with any clock frequency up to 33 MHz. The clock frequency may be
changed at any time during the operation of the system so long as the clock edges remain clean (monotonic) and the minimum cycle
and high and low times are not violated. If the clock is stopped, it must be in a low state. A variance on this specification is allowed
for the CardBus PC Card adapter which may operate the CardBus PC Card interface at any single fixed frequency up to 33 MHz,
and may enforce a policy of no frequency changes.
8. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum
peak-to-peak portion of the clock waveform (see Figure 9–2).
0.4 V
CC,
p-to-p
(Minimum)
0.325 V
CC
0.4 V
CC
0.475 V
CC
0.2 V
CC
0.6 V
CC
t
low
t
high
t
cyc
Figure 9–2. CardBus PC Card Clock Waveform
9.8.2 3.3-V Timing Parameters
MIN MAX UNIT
t
val
CCLK-to-signal-valid delay (see Notes 9 and 10) 2 18 ns
t
on
Float-to-active delay (see Note 9) 2 ns
t
off
Active-to-float delay (see Note 9) 28 ns
t
su
Input set up time to CCLK (see Note 11) 7 ns
t
h
Input hold time from CCLK (see Note 11) 0 ns
t
rst
Reset active time after power stable (see Note 12) 1 ms
t
rst-clk
Reset active time after CCLK stable (see Note 12) 100 clocks
t
rst-off
Reset-active-to-output-float delay (see Notes 12 and 13) 40 ns
t
pulse
CSTSCHG remote wakeup pulse width (see Note 14) 1 ms
NOTES: 9. t
val
includes the time to propagate data from internal registers to the output buffer and drive the output to a valid level. Minimum t
val
is measured from CCLK crossing V
test
to the signal crossing V
IH
on falling edges and V
IL
on rising edges. Maximum t
val
is measured
from CCLK crossing V
test
to the signal’s last transition out of the threshold region (V
IL
for falling edges, V
IH
for rising edges).
10. Minimum times are specified with 0-pF equivalent load; maximum times are specified with 30-pF equivalent load. Actual test
capacitance may vary, but results must be correlated to these specifications. Systems which exceed this capacitance, due to long
traces between the socket and adaptor, must reduce the CCLK frequency appropriately.
11. t
su
and t
h
are measured at V
TH
for rising edges and V
TL
for falling edges.
12. CRST
is asserted asynchronously and negated synchronously with respect to CCLK. CCLK Stable means that V
cc
is within
tolerances and CCLK is meeting specifications.
13. See PC Card Standard— Electrical Specification for the CardBus PC Card and adapter signals which must be in a high-impedance
state.
14. This parameter only applies when signaling remote wakeup over the CSTSCHG terminal. All other status change information must
be signaled by asserting CSTSCHG until the resultant interrupt is serviced.