Datasheet

1–2
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the
TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely
supplied twisted-pair bias voltage.
The TSB43AB22A device provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The
PHY layer contains two independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote
receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external
filter capacitor of 1.0 µF.
The line drivers in the TSB43AB22A device operate in a high-impedance current mode and are designed to work with
external 112-Ω line-termination resistor networks in order to match the 110-Ω cable impedance. One network is
provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω resistors.
The midpoint of the pair of resistors that is directly connected to the TPA terminals is connected to its corresponding
TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the TPB terminals is
coupled to ground through a parallel R-C network with recommended values of 5 kΩ and 220 pF. The values of the
external line-termination resistors are designed to meet the standard specifications when connected in parallel with
the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output
current and other internal operating currents. This current-setting resistor has a value of 6.34 kΩ ±1%.
When the power supply of the TSB43AB22A device is off and the twisted-pair cables are connected, the
TSB43AB22A transmitter and receiver circuitry present a high impedance to the cable and do not load the TPBIAS
voltage at the other end of the cable.
When the device is in a low-power state (for example, D2 or D3) the TSB43AB22A device automatically enters a
low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB43AB22A device disables its internal clock generators and also disables various voltage and current reference
circuits, depending on the state of the ports (some reference circuitry must remain active in order to detect new cable
connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the ultralow-power
sleep mode) is attained when all ports are either disconnected or disabled with the port interrupt enable bit cleared.
The TSB43AB22A device exits the low-power mode when bit 19 (LPS) in the host controller control register at OHCI
offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1 or when a port event occurs which
requires that the TSB43AB22A device to become active in order to respond to the event or to notify the LLC of the
event (for example, incoming bias is detected on a suspended port, a disconnection is detected on a suspended port,
or a new connection is detected on a nondisabled port). When the TSB43AB22A device is in the low-power mode,
the internal 49.153-MHz clock becomes active (and the integrated PHY layer becomes operative) within 2 ms after
bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control
Register) is set to 1.
The TSB43AB22A device supports hardware enhancements to better support digital video (DV) and MPEG data
stream reception and transmission. These enhancements are enabled through the isochronous receive digital video
enhancements register at OHCI offset A88h (see Chapter 5, TI Extension Registers). The enhancements include
automatic timestamp insertion for transmitted DV and MPEG-formatted streams and common isochronous packet
(CIP) header stripping for received DV streams.
The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data
contexts are implemented as hardware support for the synchronization timestamp for both DV and MPEG CIP
formats. The TSB43AB22A device supports modification of the synchronization timestamp field to ensure that the
value inserted via software is not stale—that is, the value is less than the current cycle timer when the packet is
transmitted.