Datasheet

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SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
TYPE
I/O
DESCRIPTION
NAME NO.
TYPE
I/O
DESCRIPTION
LPS 24 CMOS
5 V tol
I Link power status input. This terminal is used to monitor the active/power status of the link layer
controller and to control the state of the PHY-LLC interface. This terminal should be connected to
either the V
DD
supplying the LLC through a 10 k resistor, or to a pulsed output which is active when
the LLC is powered. A pulsed signal should be used when an isolation barrier exists between the
LLC and PHY (see Figure 8).
The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6 µs (128
SYSCLK cycles), and is considered active otherwise (i.e., asserted steady high or an oscillating
signal with a low time less than 2.6 µs). The LPS input must be high for at least 21 ns in order to be
guaranteed to be observed as high by the PHY.
When the TSB41LV06A detects that LPS is inactive, it places the PHY-LLC interface into a
low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and
the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains
low for more than 26 µs (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power
disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is placed
into the disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1,
and is considered inactive if either the LPS input is inactive or the the LCtrl register bit is cleared to 0.
LREQ 3 CMOS
5 V tol
I LLC request input. The LLC uses this input to initiate a service request to the TSB41LV06A. Bus
holder is built into this terminal.
PC0
PC1
PC2
28
29
30
CMOS I Power class programming inputs. On hardware reset, these inputs set the default value of the
power-class indicated during self-ID. Programmed is done by tying the terminals high or low. Refer
to Table 9 for encoding.
PD 23 CMOS
5 V tol
I Power-down input. A high on this terminal turns off all internal circuitry except the cable-active
monitor circuits, which control the CNA output. Asserting the PD input high also activates an internal
pulldown on the RESET
terminal so as to force a reset of the internal control logic
PLLGND 94, 95 Supply PLL circuit ground terminals. These terminals should be tied together to the low impedance circuit
board ground plane.
PLLV
DD
93 Supply PLL circuit power terminals. A combination of high frequency decoupling capacitors near each
terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering
capacitors are also recommended. These supply terminals are separated from DV
DD
and AV
DD
internal to the device to provide noise isolation. They should be tied at a low impedance point on the
circuit board.
SE 42 CMOS I Test control input. This input is used in manufacturing test of the TSB41LV06A. For normal use this
terminal should be tied to GND through a 1-k pulldown resistor.
SM 43 CMOS I Test control input. This input is used in manufacturing test of the TSB41LV06A. For normal use this
terminal should be tied to GND.
SYSCLK 5 CMOS O System clock output. Provides a 49.152 MHz clock signal, synchronized with data transfers, to the
LLC.
TESTM 41 CMOS I Test control input. This input is used in manufacturing test of the TSB41LV06A. For normal use this
terminal should be tied to V
DD
.
TPA0+
TPA1+
TPA2+
TPA3+
TPA4+
TPA5+
39
55
61
67
73
88
Cable I/O
Twisted-pair cable A differential signal terminals. Board traces from each pair of positive and
negative differential signal terminals should be kept matched and as short as possible to the
TPA0−
TPA1−
TPA2−
TPA3−
TPA4−
TPA5−
38
54
60
66
72
87
Cable I/O
negative differential signal terminals should be kept matched and as short as possible to the
external load resistors and to the cable connector. For an unused port,TPA+ and TPA−can be lef
t
open.