Datasheet


    
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
TPA5+
TPA5−
TPB5+
TPB5−
XI
XO
FILTER0
FILTER1
CPS
Link
Interface
I/O
LPS
ISO
CNA
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
Received
Data
Decoder/
Retimer
Arbitration
and
Control State
Machine
Logic
PC0
PC1
PC2
C/LKON
Bias
Voltage
and
Current
Generator
R0
R1
TPBIAS0
TPBIAS1
TPBIAS2
TPBIAS3
TPBIAS4
TPBIAS5
Transmit
Data
Encoder
Crystal Oscillator,
PLL System,
and Clock
Generator
Cable Port 5
TPA4+
TPA4−
TPB4+
TPB4−
Cable Port 4
TPA3+
TPA3−
TPB3+
TPB3−
Cable Port 3
TPA2+
TPA2−
TPB2+
TPB2−
Cable Port 2
TPA1+
TPA1−
TPB1+
TPB1−
Cable Port 1
TPA0+
TPA0−
TPB0+
TPB0−
Cable Port 0
PD
RESET