Datasheet
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interface reset and disable (continued)
The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and request
activity. When the PHY observes that LPS has been deasserted for T
LPS_RESET
, it resets the interface. When
the interface is in the reset state, the PHY sets its CTL and D outputs in the logic 0 state and ignores any activity
on the LREQ signal. The timing for interface reset is shown in Figure 22 and Figure 23.
The sequence of events for resetting the PHY-LLC interface when it is in the differentiated mode of operation
(ISO
terminal is low) is as follows:1
a. Normal operation. Interface is operating normally, with LPS active, SYSCLK active, status and packet
data reception and transmission via the CTL and D lines, and request activity via the LREQ line.
b. LPS deasserted. The LLC deasserts the LPS signal and, within 1.0 µs, terminates any request or
interface bus activity, and places its LREQ, CTL, and D outputs into a high-impedance state (the LLC
should terminate any output signal activity such that signals end in a logic 0 state).
c. Interface reset. After T
LPS_RESET
time, the PHY determines that LPS is inactive, terminates any
interface bus activity, and places its CTL and D outputs into a high-impedance state (the PHY
terminates any output signal activity such that signals end in a logic 0 state). The PHY-LLC interface
is now in the reset state.
d. Interface restored. After the minimum T
RESTORE
time, the LLC may again assert LPS active. (The
minimum T
RESTORE
interval provides sufficient time for the biasing networks used in Annex J type
isolation barrier circuits to stabilize and reach a quiescent state if the isolation barrier has somehow
become unbalanced.) When LPS is asserted, the interface is initialized as described below.
SYSCL
K
ISO
(high)
(a) (c)
(b)
CTL0, CTL1
D0 − D7
LREQ
LPS
(d)
T
LPS_RESET
T
RESTORE
Figure 23. Interface Reset, ISO High