Datasheet

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    

SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

receive (continued)

(a)

(b) (c)

FF (“data-on”)

D0–D7

CTL0, CTL1

SYSCLK

Figure 19. Null Packet Reception Timing

The sequence of events for a null packet reception is as follows:1

a. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL

lines. Normally, the interface is idle when receive is asserted. However, the receive operation may

interrupt a status transfer operation that is in progress so that the CTL lines may change from status

to receive without an intervening idle.

b. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.

c. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL

lines. The PHY shall assert at least one cycle of idle following a receive operation.

Table 20. Receive Speed Codes

D0–D7 DATA RATE

00XX XXXX S100

0100 XXXX S200

0101 0000 S400

1YYY YYYY “data−on” indication

NOTE: X = Output as 0 by PHY, ignored by LLC.

Y = Output as 1 by PHY, ignored by LLC

transmit

When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus.

If the PHY wins arbitration for the serial bus, the PHY-LLC interface bus is granted to the LLC by asserting the

grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by idle for one clock cycle. The LLC then

takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. Unless

the LLC is immediately releasing the interface, the LLC may assert the idle state for at most one clock before

it must assert either hold or transmit on the CTL terminals. The hold state is used by the LLC to retain control

of the bus while it prepares data for transmission. The LLC may assert hold for zero or more clock cycles (i.e.,

the LLC need not assert hold before transmit). The PHY asserts data-prefix on the serial bus during this time.