Datasheet


    
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
35
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
receive (continued)
It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed
by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds
the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any
data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D
terminals, followed by idle on the CTL terminals, without any speed code or data being transferred. In all cases,
the TSB41LV06A sends at least one data-on indication before sending the speed code or terminating the
receive operation.
The TSB41LV06A also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization,
to the LLC. This packet it transferred to the LLC just as any other received self-ID packet.
00
0010
XX dnd0SPD
(a)
(b)
FF (“data-on”)
D0–D7
CTL0, CTL1
SYSCLK
(c) (d)
(e)
NOTE A: SPD = Speed code, see Table 20 d0–dn = Packet data
00
01
Figure 18. Normal Packet Reception Timing
The sequence of events for a normal packet reception is as follows:1
a. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL
lines. Normally, the interface is idle when receive is asserted. However, the receive operation may
interrupt a status transfer operation that is in progress so that the CTL lines may change from status
to receive without an intervening Idle.
b. Data-on indication. The PHY may assert the data-on indication code on the D lines for zero or more
cycles preceding the speed-code.
c. Speed-code. The PHY indicates the speed of the received packet by asserting a speed-code on the
D lines for one cycle immediately preceding packet data. The link decodes the speed-code on the first
receive cycle for which the D lines are not the data-on code. If the speed-code is invalid, or indicates
a speed higher that that which the link is capable of handling, the link should ignore the subsequent data.
d. Receive data. Following the data-on indication (if any) and the speed-code, the PHY asserts packet
data on the D lines with receive on the CTL lines for the remainder of the receive operation.
e. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL
lines. The PHY asserts at least one cycle of idle following a receive operation.