Datasheet


    
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
34
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
status transfer (continued)
The definition of the bits in the status transfer are shown in Table 19 and the timing is shown in Figure 17.
Table 19. Status Bits
BIT(s) NAME DESCRIPTION
0 Arbitration reset gap Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as defined in
the IEEE 1394−1995 standard). This bit is used by the LLC in the busy/retry state machine.
1 Subaction gap Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in the
IEEE 1394−1995 standard). This bit is used by the LLC to detect the completion of an isochronous cycle.
2 Bus reset Indicates that the PHY has entered the bus reset state.
3 Interrupt Indicates that a PHY interrupt event has occurred. An interrupt event may be a configuration time-out,
cable-power voltage falling too low, a state time-out, or a port status change.
4−7 Address This field holds the address of the PHY register whose contents are being transferred to the LLC.
8−15 Data This field holds the register contents.
00
(a)
01
(b)
00
00 S[14:15]S[0:1]
D0, D1
CTL0, CTL1
SYSCLK
00
Figure 17. Status Transfer Timing
The sequence of events for a status transfer is as follows:
1. Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along with
the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle). Normally (unless
interrupted by a receive operation), a status transfer is either 2 or 8 cycles long. A 2-cycle (4 bit) transfer
occurs when only status information is to be sent. An 8-cycle (16 bit) transfer occurs when register data is
to be sent in addition to any status information.
2. Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines.
The PHY may also interrupt a status transfer at any cycle by asserting receive on the CTL lines to begin
a receive operation. The PHY asserts at least one cycle of idle between consecutive status transfers.
receive
Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting
Receive on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The PHY indicates
the start of a packet by placing the speed code (encoded as shown in Table 20 on the D terminals, followed by
packet data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet has been
transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All received
packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included
in the calculation of CRC or any other data protection mechanisms.