Datasheet

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SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
LLC service request (continued)
Regardless of the type of request, a start-bit of 1 is required at the beginning of the stream, and a stop-bit of
0 is required at the end of the stream. The second through fourth bits of the request stream indicate the type
of the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit
stream. The LREQ terminal is normally low.
Encoding for the request type is shown in Table 13.
Table 13. Request Type Encoding
LR1–LR3 NAME DESCRIPTION
000 ImmReq Immediate bus request. Upon detection of idle, the PHY takes control of the bus immediately without arbitration.
001 IsoReq Isochronous bus request. Upon detection of idle, the PHY arbitrates for the bus without waiting for a subaction gap.
010 PriReq Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol.
011 FairReq Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol.
100 RdReg The PHY returns the specified register contents through a status transfer.
101 WrReg Write to the specified register.
110 AccelCtl Enable or disable asynchronous arbitration acceleration.
111 Reserved Reserved
For a Bus Request the length of the LREQ bit stream is 7 or 8 bits as shown in Table 14.
Table 14. Bus Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1).
1-3 Request type Indicates the type of bus request. See Table 13.
4-6 Request speed Indicates the speed at which the PHY sends the data for this request. See Table 15 for the encoding of this field.
7 Stop bit Indicates the end of the transfer (always 0). If bit 6 is 0, this bit may be omitted.
The 3-bit request speed field used in bus requests is shown in Table 15.
Table 15. Bus Request Speed Encoding
LR4–LR6 DATA RATE
000 S100
010 S200
100 S400
All Others Invalid
NOTE:
The TSB41LV06A accepta a bus request with an invalid speed code and process the bus request
normally. However, during packet transmission for such a request, the TSB41LV06A ignores any
data presented by the LLC and transmits a null packet.