Datasheet


    
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
The TSB41LV06A implements differentiation circuitry functionally equivalent to that shown in Figure 15 on the
bidirectional CTL0–CTL1and D0–D7 terminals. The TSB41LV06A also implements an input hysteresis buffer
on the LREQ input to convert this signal to the correct logic level when differentiated. The LLC must also
implement similar output differentiation and input hysteresis circuitry on its CTL and D terminals and output
differentiation circuitry on its LREQ terminal.
DIn
To/From
Internal
Device
Logic
DOut
ISO
OutEn
Init
SysClk
DQ
D
QD
QD
3-State
Output
Driver
Input BUffer With Hysteresis
Figure 15. Input/Output Differentiation Logic
LLC service request
To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC sends
a serial bit stream on the LREQ terminal as shown in Figure 13.
NOTE: Each cell represents one clock sample time, and n is the number of bits in the request stream.
LR1
LR2 LR3 LR (n−2)LR0 LR (n−1)
Figure 16. LREQ Request Stream
The length of the stream varies depending on the type of request as shown in Table 12.
Table 12. LLC Request Stream Bit Length
REQUEST TYPE NUMBER OF BITS
Bus request 7 or 8
Read register request 9
Write register request 17
Acceleration control request 6