Datasheet
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
27
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APPLICATION INFORMATION
crystal selection (continued)
C10
X1
C9
Figure 12. Recommended Crystal and Capacitor Layout
It is strongly recommended that part of the verification process for the design be to measure the frequency of
the SYSCLK output of the PHY. This should be done with a frequency counter with an accuracy of 6 digits or
better. If the SYSCLK frequency is more than the crystal’s tolerance from 49.152 MHz, the load capacitance
of the crystal may be varied to improve frequency accuracy. If the frequency is too high add more load
capacitance; if the frequency is too low decrease load capacitance. Typically, changes should be done to both
load capacitors (C9 and C10 above) at the same time, and both should be of the same value. Additional design
details and requirements may be provided by the crystal vendor.
bus-reset
In the TSB41LV06A, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus-reset and initialization
sequence. The IBR bit is located in PHY register 1, along with the root-holdoff (RHB) bit and gap-count register,
as required by the P1394a Supplement (this configuration also maintains compatibility with older TI PHY
designs which were based upon the suggested register set defined in Annex J of IEEE Std 1394-1995).
Therefore, whenever the IBR bit is written, the RHB bit and gap-count are also necessarily written.
The RHB bit and gap-count may also be updated by PHY-config packets. The TSB41LV06A is P1394a
compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and
gap-count to be loaded, unlike older IEEE Std 1394-1995 compliant PHYs which decode only received
PHY-config packets.
The gap-count is set to the maximum value of 63 after two consecutive bus-resets without an intervening write
to the gap-count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a
PHY-config packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have
updated their RHB bits and gap-count values, without having the gap-count set back to 63 by the bus reset. The
subsequent connection of a new node to the bus, which initiates a bus-reset, then causes the gap-count of each
node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1
to set the IBR bit, all other nodes on the bus have their gap-count values set to 63, while this node’s gap-count
remains set to the value just loaded by the write to PHY register 1.
Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use
of the IBR bit, RHB bit, and gap-count in PHY register 1:
1. Following the transmission of a PHY-config packet, a bus-reset must be initiated in order to verify that all
nodes have correctly updated their RHB bits and gap-count values, and to ensure that a subsequent new
connection to the bus causes the gap-count to be set to 63 on all nodes in the bus. If this bus-reset is initiated
by setting the IBR bit to 1, the RHB bit and gap-count register must also be loaded with the correct values
consistent with the just transmitted PHY-config packet. In the TSB41LV06A, the RHB bit and gap-count is
updated to their correct values upon the transmission of the PHY-config packet, and so these values may
first be read from register 1 and then rewritten.
2. Other than to initiate the bus-reset which must follow the transmission of a PHY-config packet, whenever
the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to 63 so as to be
consistent with other nodes on the bus, and the RHB bit should be maintained with its current value.
3. The PHY register 1 should not be written to except to set the IBR bit. The RHB bit and gap-count should
not be written without also setting the IBR bit to 1.