Datasheet
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
using the TSB41LV06A with a lower-speed link layer (continued)
To assist in building an accurate speed-map, the TSB41LV06A has the capability of indicating a speed capability
other than S400 in its transmitted self-ID packet. This is controlled by the Link_Speed field in register 8 of the
Vendor-Dependent page (page 7). Setting the Link_Speed field affects only the speed indicated in the self-ID
packet; it has no effect on the speed signaled to peer PHYs during self-ID. The TSB41LV06A identifies itself
as S400 capable to its peers regardless of the value in the Link_Speed field.
Generally, the Link_Speed field should not be changed from its power-on default value of S400 unless it is
determined that the speed-map (if one exists) is incorrect for path entries terminating in the local node. If the
speed-map is incorrect, it can be assumed that the bus manager has used only the self-ID packet information
to build the speed-map. In this case, the node may update the Link_Speed field to reflect the lower speed
capability of the LLC and then initiate another bus-reset to cause the speed-map to be rebuilt. Note that in this
scenario any speed-map entries for node-to-node communication paths that pass through the local node’s PHY
is restricted by the lower speed.
In the case of a leaf node (which has only one active port) the Link_Speed field may be set to indicate the speed
of the LLC without first checking the speed−map. Changing the Link_Speed field in a leaf node can only affect
those paths that terminate at that node, since no other paths can pass through a leaf node. It can have no effect
on other paths in the speed-map. For hardware configurations, which can only be a leaf node (all ports but one
are unimplemented), it is recommended that the Link_Speed field be updated immediately after power-on or
hardware reset.
power-up reset
To ensure proper operation of the TSB41LV06A the RESET terminal must be asserted low for a minimum of
2 ms from the time that PHY power reaches the minimum required supply voltage. When using a passive
capacitor on the RESET
terminal to generate a power-on reset signal, the minimum reset time is assured if the
capacitor has a minimum value of 0.1 µF and also satisfies the following equation:
C
min
= 0.0077 × T + 0.085
where C
min
is the minimum capacitance on the RESET terminal in µF, and T is the V
DD
ramp time, 10%–90%,
in ms.
crystal selection
The TSB41LV06A and other TI PHY devices are designed to use an external 24.576 MHz crystal connected
between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn
drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data
at the S100 through S400 media data rates.
A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent
PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must
be able to compensate for this difference over the maximum packet length. Larger clock variations may cause
resynchronization overflows or underflows, resulting in corrupted packet data.
For the TSB41LV06A, the SYSCLK output may be used to measure the frequency accuracy and stability of the
internal oscillator and PLL from which it is derived. The frequency of the SYSCLK output must be within
±100 ppm of the nominal frequency of 49.152 MHz.