Datasheet
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
23
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APPLICATION INFORMATION
designing with PowerPAD
The TSB41LV06A is housed in a high performance, thermally enhanced, 100-pin PZP PowerPAD package. Use
of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which
is an exposed metallic pad on the bottom of the device, is a thermal and electrical conductor. This exposed pad
is connected internally to the package to the substrate of the silicon die; it is not connected to any terminal of
the package. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other
assembly techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of
connection etches or vias under the package. The recommended option, however, is to not run any etches or
signal vias under the device, but to have only a grounded thermal land as explained below. Although the actual
size of the exposed die pad may vary, the minimum size required for the keepout area for the 100-pin PZP
PowerPAD package is 12 mm × 12 mm.
It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the
PowerPAD package. The thermal land varies in size depending on the PowerPAD package being used, the PCB
construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not
contain numerous thermal vias depending on PCB construction.
Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD
Thermally Enhanced Package Application Report, TI literature number SLMA002, available via the TI Web
pages beginning at URL: http://www.ti.com.
Figure 10. Example of a Thermal Land for the TSB41LV06A PHY
For the TSB41LV06A, this thermal land should be grounded to the low impedance ground plane of the device.
This improves not only thermal performance but also the electrical grounding of the device. It is also
recommended that the device ground terminal landing pads be connected directly to the grounded thermal land.
The land size should be as large as possible without shorting device signal terminals. The thermal land may
be soldered to the exposed PowerPAD using standard reflow soldering techniques.
While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is
recommended that the thermal land be connected to the low impedance ground plane for the device. More
information may be obtained from the TI application note PHY Layout, TI literature number SLLA020.
using the TSB41LV06A with a non-P1394a link layer
The TSB41LV06A implements the PHY-LLC interface specified in the P1394a Supplement. This interface is
based upon the interface described in informative Annex J of IEEE Std 1394−1995, which is the interface used
in older TI PHY devices. The PHY-LLC interface specified in P1394a is completely compatible with the older
Annex J interface.