Datasheet

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SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
19
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table 7. Page 7 (Vendor Dependent) Register Configuration
ADDRESS
BIT POSITION
ADDRESS
0 1 2 3 4 5 6 7
1000 NPA Reserved Link_Speed
1001 Reserved for test
1010 Reserved for test
1011 Reserved for test
1100 Reserved for test
1101 Reserved for test
1110 Reserved for test
1111 Reserved for test
Table 8. Page 7 (Vendor Dependent) Register Field Descriptions
FIELD SIZE TYPE DESCRIPTION
NPA 1 Rd/Wr Null-packet actions flag. This bit instructs the PHY to not clear fair and priority requests when a null packet is
received with arbitration acceleration enabled. If 1, then fair and priority requests are cleared only when a
packet of more than 8 bits is received; ACK packets (exactly 8 data bits), null packets (no data bits), and
malformed packets (less than 8 data bits) do not clear fair and priority requests. If 0, then fair and priority
requests are cleared when any non-ACK packet is received, including null-packets or malformed packets of
less than 8 bits. This bit is cleared to 0 by hardware reset and is unaffected by bus-reset.
Link_Speed 2 Rd/Wr Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:
Code Speed
00 S100
01 S200
10 S400
11 illegal
This field is replicated in the sp field of the self-ID packet to indicate the speed capability of the node (PHY and
LLC in combination). However, this field does not affect the PHY speed capability indicated to peer PHYs
during self-ID; the TSB41LV06A PHY identifies itself as S400 capable to its peers regardless of the value in
this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus-reset.
power-class programming
The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field
(bits 21–23) of the transmitted self-ID packet. Descriptions of the various power-classes are given in Table 9
The default power-class value is loaded following a hardware reset, but is overridden by any value subsequently
loaded into the Pwr_Class field in register 4.
Table 9. Power-Class Description
PC0–PC2 DESCRIPTION
000 Node does not need power and does not repeat power.
001 Node is self-powered and provides a minimum of 15 W to the bus.
010 Node is self-powered and provides a minimum of 30 W to the bus.
011 Node is self-powered and provides a minimum of 45 W to the bus.
100 Node may be powered from the bus for the PHY only using up to 3W and may also provide power to the bus. The amount of bus
power that it provides can be found in the configuration ROM.
101 Node is powered from the bus and uses up to 3 W. An additional 2 W is needed to enable the link and higher layers of the node.
110 Node is powered from the bus and uses up to 3W. An additional 3W is needed to enable the link.
111 Node is powered from the bus and uses up to 3W. An additional 7W is needed to enable the link.