Datasheet
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table 2. Base Register Field Descriptions
FIELD SIZE TYPE DESCRIPTION
Physical ID 6 Rd This field contains the physical address ID of this node determined during self-ID. The physical-ID is invalid
after a bus-reset until self-ID has completed as indicated by an unsolicited register-0 status transfer.
R 1 Rd Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus-reset, and is set to 1 during
tree-ID if this node becomes root.
CPS 1 Rd Cable-power-status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied
to serial bus cable power through a 400-kΩ resistor. A 0 in this bit indicates that the cable power voltage has
dropped below its threshold for ensured reliable operation.
RHB 1 Rd/Wr Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus-reset. The RHB bit is
reset to 0 by hardware reset and is unaffected by bus-reset.
IBR 1 Rd/Wr Initiate bus-reset. This bit instructs the PHY to initiate a long (166 µs) bus-reset at the next opportunity. Any
receive or transmit operation in progress when this bit is set completes before the bus-reset is initiated. The
IBR bit is reset to 0 by hardware reset or bus-reset.
Gap_Count 6 Rd/Wr Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay times.
The gap count may be set either by a write to this register or by reception or transmission of a PHY_CONFIG
packet. The gap count is set to 3Fh by hardware reset or after two consecutive bus-resets without an
intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG packet).
Extended 3 Rd Extended register definition. For the TSB41LV06A this field is 111b, indicating that the extended register set is
implemented.
Num_Ports 4 Rd Number of ports. This field indicates the number of ports implemented in the PHY. For the TSB41LV06A this
field is 6.
PHY_Speed 3 Rd PHY speed capability. For the TSB41LV06A PHY this field is 010b, indicating S400 speed capability.
Delay 4 Rd PHY repeater data delay. This field indicates the worst case repeater data delay of the PHY, expressed as
144+(delay × 20) ns. For the TSB41LV06A this field is 0.
LCtrl 1 Rd/Wr Link-active status control. This bit is used to control the active status of the LLC as indicated during self-ID.
The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The
LLC is considered active only if both the LPS input is active and the LCtrl bit is set.
The LCtrl bit provides a software controllable means to indicate the LLC active status in lieu of using the LPS
input.
The LCtrl bit is set to 1 by hardware reset and is unaffected by bus-reset.
NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the
LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, then received
packets and status information continues to be presented on the interface, and any requests indicated on the
LREQ input are processed, even if the LCtrl bit is cleared to 0.
C 1 Rd/Wr Contender status. This bit indicates that this node is a contender for the bus or isochronous resource
manager. This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to the state specified by
the C/LKON input terminal upon hardware reset and is unaffected by bus-reset.
Jitter 3 Rd PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest repeater
data delay, expressed as (JITTER+1) × 20 ns. For the TSB41LV06A this field is 0.
Pwr_Class 3 Rd/Wr Node power class. This field indicates this node’s power consumption and source characteristics, and is
replicated in the pwr field (bits 21–23) of the self-ID packet. This field is set to the state specified by the
PC0−PC2 input terminals upon hardware reset and is unaffected by bus-reset. See Table 9.
RPIE 1 Rd/Wr Resuming port interrupt enable. This bit, if set to 1, enables the port event interrupt (PIE) bit to be set
whenever resume operations begin on any port. This bit is reset to 0 by hardware reset and is unaffected by
bus-reset.
ISBR 1 Rd/Wr Initiate short arbitrated bus-reset. This bit, if set to 1, instructs the PHY to initiate a short (1.30 µs) arbitrated
bus-reset at the next opportunity. This bit is reset to 0 by bus-reset.
NOTE: Legacy IEEE Std 1394-1995 compliant PHYs may not be capable of performing short bus-resets.
Therefore, initiation of a short bus-reset in a network that contains such a legacy device results in a long
bus-reset being performed.