Datasheet

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    
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
thermal characteristics
PARAMETER TEST CONDITION
†
MIN TYP MAX UNIT
R
θJA
Junction-to-free-air thermal resistance
Board mounted, No air flow,
High conductivity TI recommended test board,
17.85
°C/W
R
θJC
Junction-to-case-thermal resistance
High conductivity TI recommended test board,
Chip soldered or greased to thermal land with 1 oz.
copper
0.12
°
C/W
R
θJA
Junction-to-free-air thermal resistance
Board mounted, No air flow,
High conductivity TI recommended test board with
28.22
°C/W
R
θJC
Junction-to-case-thermal resistance
High conductivity TI recommended test board with
thermal land but no solder or grease thermal
connection to thermal land with 1 oz. copper
0.12
°
C/W
R
θJA
Junction-to-free-air thermal resistance
Board mounted, No air flow,
High conductivity JEDEC test board with 1 oz.
49.17
°C/W
R
θJC
Junction-to-case-thermal resistance
High conductivity JEDEC test board with 1 oz.
copper
3.11
°
C/W
†
Usage of thermally enhanced PowerPad PZP package is assumed in all three test conditions.
switching characteristics
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Jitter, transmit Between TPA and TPB ±0.15 ns
Skew, transmit Between TPA and TPB ±0.10 ns
t
r
TP differential rise time, transmit 10% to 90%, At 1394 connector 0.5 1.2 ns
t
f
TP differential fall time, transmit 90% to 10%, At 1394 connector 0.5 1.2 ns
t
su
Setup time, CTL0, CTL1, D0−D7, LREQ to SYSCLK 50% to 50% See Figure 2 5 ns
t
h
Hold time, CTL0, CTL1, D0−D7, LREQ after SYSCLK 50% to 50% See Figure 2 2 ns
t
d
Delay time, SYSCLK to CTL0, CTL1, D0−D7 50% to 50% See Figure 3 2
‡
ns
‡
Test Conditions: 3.3 V
CC
, T
A
= 25°C
PARAMETER MEASUREMENT INFORMATION
TPAx+
TPBx+
TPAx−
TPBx−
56 Ω
Figure 1. Test Load Diagram
SYSCLK
Dx, CTLx, LREQ
t
su
t
h
Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms