Datasheet

00
0010
XX dnd0SPD
(a) (b)
FF (data-on)D0–D7
CTL0, CTL1
PCLK
(c) (d)
(e)
00
0010
XX dnd0SPD
(a) (b)
FF (data-on)D0–D7
CTL0, CTL1
PCLK
(c) (d)
(e)
01
STATUS
10
FF
(data-on)
TSB41BA3D
SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com
The PHY can optionally send status information to the LLC at anytime during the data-on indication. Only bus
status transfer information can be sent during a data-on indication. The PHY holds the CTL terminals in the
status state for 1 PCLK cycle and modifies the D terminals to the correct status state. Note that the status
transfer during the data-on indication does not need to be preceded or followed by a data-on indication.
It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus
followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed
exceeds the capability of the receiving PHY, or whenever the LLC immediately releases the bus without
transmitting any data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all
1s) on the D terminals, followed by idle on the CTL terminals, without any speed code or data being transferred.
In all cases, in normal operation, the TSB41BA3D sends at least one data-on indication before sending the
speed code or terminating the receive operation.
The TSB41BA3D also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization, to
the LLC. This packet it transferred to the LLC just as any other received self-ID packet.
A. SPD = speed code, see Table 38 . d0 – dn = packet data.
Figure 26. Normal Packet Reception Timing
A. SPD = speed code, see Table 38 . d0 – dn = packet data. STATUS = status bits, see Table 35 .
Figure 27. Normal Packet Reception Timing With Optional Bus Status Transfer
The sequence of events for a normal packet reception is as follows:
a. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.
Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a status
transfer operation that is in progress so that the CTL lines can change from status to receive without an
intervening idle.
b. Data-on indication. The PHY can assert the data-on indication code on the D lines for one or more cycles
preceding the speed code. The PHY can optionally send a bus status transfer during the data-on indication
for one PCLK cycle. During this cycle, the PHY asserts status (01b) on the CTL lines while sending status
information on the D lines.
c. Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D lines
for one cycle immediately preceding packet data. The link decodes the speed code on the first receive cycle
for which the D lines are not the data-on code. If the speed code is invalid or indicates a speed higher than
that which the link is capable of handling, then the link must ignore the subsequent data.
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