Datasheet

Status Transfer
D[0:7]
XX ST XX
CTL[0:1]
XX 01 XX
Status Bits
TSB41BA3D
SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com
To send an acknowledge packet, the LLC must issue an immediate bus request (Immed_Req) during the
reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of the
received packet and the start of the transmitted acknowledge packet. As soon as the received packet ends, the
PHY immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless
the header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but
instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant to
send another type of packet. After the interface is released the LLC can proceed with another request.
For write register requests, the PHY loads the specified data into the addressed register as soon as the request
transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the
LLC at the next opportunity through a PHY status transfer. A write or read register request can be made at any
time, including while a bus request is pending. Once a read register request is made, the PHY ignores further
read register requests until the register contents are successfully transferred to the LLC. A bus reset does not
clear a pending read register request.
A status transfer is initiated by the PHY when status information is to be transferred to the LLC. Two types of
status transfers can occur: bus status transfer and PHY status transfer. Bus status transfers send the following
status information: bus reset indications, subaction and arbitration reset gap indications, cycle start indications,
and PHY interface reset indications. PHY status transfers send the following information: PHY interrupt
indications, unsolicited and solicited PHY register data, bus initialization indications, and PHY-link interface error
indications. The PHY uses a different mechanism to send the bus status transfer and the PHY status transfer.
Bus status transfers use the CTL0 – CTL1 and D0 – D7 terminals to transfer status information. Bus status
transfers can occur during idle periods on the PHY-link interface or during packet reception. When the status
transfer occurs, a single PCLK cycle of status information is sent to the LLC. The information is sent such that
each individual Dn terminal conveys a different bus status transfer event. During any bus status transfer, only
one status bit is set. If the PHY-link interface is inactive, then the status information is not sent. When a bus reset
on the serial bus occurs, the PHY sends a bus reset indication (via the CTLn and Dn terminals), cancels all
packet transfer requests, sets asynchronous and isochronous phases to even, forwards self-ID packets to the
link, and sends an unsolicited PHY register 0 status transfer (via the PINT terminal) to the LLC. In the case of a
PHY interface reset operation, the PHY-link interface is reset on the following PCLK cycle.
Table 35 shows the definition of the bits during the bus status transfer and Figure 24 shows the timing.
Table 35. Status Bits
STATUS BIT DESCRIPTION
D0 Bus reset
D1 Arbitration reset gap — odd
D2 Arbitration reset gap — even
D3 Cycle start — odd
D4 Cycle start — even
D5 Subaction gap
D6 PHY interface reset
D7 Reserved
Figure 24. Bus Status Transfer Timing
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