Datasheet

TSB41BA3D
www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009
Table 31. Bus Request Speed Encoding
LR6 – LR9 DATA RATE
0000 S100
0001 Reserved
0010 S200
0011 Reserved
0100 S400
0101 Reserved
0110 S800
All Others Invalid
NOTE:
The TSB41BA3D accepts a bus request with an invalid speed code and processes
the bus request normally. However, during packet transmission for such a request, the
TSB41BA3D ignores any data presented by the LLC and transmits a null packet.
For a read register request, the length of the LREQ bit stream is 10 bits as shown in Table 32 .
Table 32. Read Register Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1 – 4 Request type A 1010 indicates this is a read register request.
5 – 8 Address Identifies the address of the PHY register to be read
9 Stop bit Indicates the end of the transfer (always 0)
For a write register request, the length of the LREQ bit stream is 18 bits as shown in Table 33 .
Table 33. Write Register Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1 – 4 Request type A 1011 indicates this is a write register request.
5 – 8 Address Identifies the address of the PHY register to be written
9 – 16 Data Gives the data that is to be written to the specified register address
17 Stop bit Indicates the end of the transfer (always 0)
For a link notification request, the length of the LREQ bit stream is 6 bits as shown in Table 34 .
Table 34. Link Notification Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1 – 4 Request type A 1100, 1101, or 1110 indicates this is a link notification request
5 Stop bit Indicates the end of the transfer (always 0)
For fair or priority access, the LLC sends a bus request at least one clock after the PHY-LLC interface becomes
idle. The PHY queues all bus requests and can queue one request of each type. If the LLC issues a different
request of the same type, then the new request overwrites any nonserviced request of that type. On the receipt
(CTL terminals are asserted to the receive state, 10b) of a packet, queued requests are not cleared by the PHY.
The cycle master node uses a cycle start request (Cyc_Start_Req) to send a cycle start message. After receiving
or transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears
an isochronous request only when the serial bus has been won.
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